Block contact architectures for nanoscale channel transistors

• US 7,279,375 B2
• Filed: 06/30/2005
• Issued: 10/09/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Radosavljevic, Marko, Doczy, Mark L., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Majumdar, Amlan, Datta, Suman
• Primary Examiner(s): Nguyen; Tuan H.
• Application Number:
  US11/173,866
• Publication Number:
  US 20070001219A1
• Time in Patent Office: 831 Days
• Field of Search: 438/197, 438/151, 438/156, 438/157
• US Class Current: 438/197
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Claims

1. A method of forming a semiconductor device comprising:

forming a plurality of parallel semiconductor bodies, wherein each of said semiconductor bodies has a channel region between a source region and a drain region;

forming a single gate electrode over and adjacent to said channel regions of said plurality of parallel semiconductor bodies;

forming a dielectric layer over said gate electrode and said plurality of parallel semiconductor bodies;

forming a single drain opening in said dielectric layer which extends between and exposes said drain regions of said plurality of parallel semiconductor bodies;

forming a single source opening in said dielectric layer which extends between and exposes said source regions of said plurality of parallel semiconductor bodies, wherein forming the single drain opening and single source opening in said dielectric layer further comprises exposing a photoresist mask to approximate one-dimensional slots having a lithographically defined length that is substantially smaller than the lithographically defined width; and

filling said single drain opening and said single source opening with a metal film wherein said metal film is in contact with said source regions and said drain regions of said plurality of parallel semiconductor bodies.

2. The method of claim 1 wherein said plurality of parallel semiconductor bodies is formed by a method comprising:

forming a first pattern of parallel features having a first pitch from a first material,

blanket depositing a conformal film of a second material over and adjacent to said first pattern of parallel features; and

anisotropically etching said conformal film to form a plurality of parallel spacers from said second material;

said plurality of parallel spacers having a second pitch less than said first pitch;

removing said first pattern of parallel features of said first material and etching a semiconductor film in alignment with said plurality of parallel spacers to form the plurality of parallel semiconductor bodies.

3. The method of claim 2 wherein said first pattern of parallel features are formed by forming a photoresist mask over said first material, and anisotropically etching said first material in alignment with said photoresist mask.

4. The method of claim 3 wherein said photoresist mask is formed by blanket depositing a photoresist film and patterning said photoresist film into a plurality of parallel features having said second pitch which is the smallest pitch which can be defined in said photoresist film utilizing a photolithography process.

5. The method of claim 1 wherein said metal film is blanket deposited into said source opening and said drain opening and onto the top surface of said dielectric layer;

and

polishing back said metal film from the top surface of said dielectric layer to form a single drain contact and a single source contact.

6. The method of claim 5 wherein said metal film is formed in said opening utilizing an electroless or electrolytic deposition process.

7. The method of claim 1, wherein forming a single drain opening in said dielectric layer further comprises exposing a sidewall of said drain regions of said plurality of parallel semiconductor bodies.

8. The method of claim 1, wherein filling said single drain opening with a metal film further comprises depositing a metal on the exposed sidewall of said drain regions of said plurality of parallel semiconductor bodies.

9. A method of forming a semiconductor device comprising:

forming a plurality of semiconductor bodies in a parallel orientation, wherein each semiconductor body has a channel region between a source region and a drain region;

forming a single gate electrode over and adjacent to each channel region of the plurality;

forming a dielectric layer over the gate electrode and plurality of parallel semiconductor bodies;

forming a first source opening in the dielectric layer exposing a sidewall of at least two of the source regions;

forming a second source opening in the dielectric layer exposing a sidewall of at least two of the source regions not exposed by the first source opening;

filling said first source opening with a metal film in contact with the exposed sidewalls to form a first source contact electrically coupling in parallel the at least two source regions exposed by the first source opening;

filling said second source opening with a metal film in contact with the exposed sidewalls to form a second source contact electrically coupling in parallel the at least two source regions exposed by the second source opening;

forming a drain opening in said dielectric exposing both the drain region of the semiconductor bodies having source regions electrically coupled to the first source contact and the drain region of the semiconductor bodies having source regions electrically coupled to the second source contact;

filling said drain opening with a metal film in contact with the exposed drain regions to form a drain contact electrically coupling in parallel the drain regions exposed by the drain opening.

10. The method of claim 9, wherein the drain opening further exposes a sidewall of the drain region of a semiconductor body having a source region not electrically coupled to either the first or second source contact.

11. A method of forming a semiconductor device comprising:

forming a plurality of semiconductor bodies in a parallel orientation, wherein each semiconductor body has a channel region between a source region and a drain region;

forming a single gate electrode over and adjacent to each channel region of the plurality;

forming a dielectric layer over the gate electrode and plurality of parallel semiconductor bodies;

forming a first drain opening in the dielectric layer exposing a sidewall of at least two of the drain regions;

forming a second drain opening in the dielectric layer exposing a sidewall of at least two of the drain regions not exposed by the first drain opening;

filling said first drain opening with a metal film in contact with the exposed sidewalls to form a first drain contact electrically coupling in parallel the at least two drain regions exposed by the first drain opening;

filling said second drain opening with a metal film in contact with the exposed sidewalls to form a second drain contact electrically coupling in parallel the at least two drain regions exposed by the second drain opening;

forming a source opening in said dielectric exposing both the source region of the semiconductor bodies having drain regions electrically coupled to the first drain contact and the source region of the semiconductor bodies having drain regions electrically coupled to the second drain contact;

filling said first source opening with a metal film in contact with the exposed source regions to form a first source contact electrically coupling in parallel the source regions exposed by the source opening.

12. The method of claim 11, wherein the source opening further exposes a sidewall of the source region of a semiconductor body having a drain region not electrically coupled to either the first or second drain contact.