Method and structure for shallow trench isolation during integrated circuit device manufacture

• US 7,279,377 B2
• Filed: 08/10/2005
• Issued: 10/09/2007
• Est. Priority Date: 08/10/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej, Rueger, Neal R.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US11/200,694
• Publication Number:
  US 20070037341A1
• Time in Patent Office: 790 Days
• Field of Search: 438/222, 438/296, 438/FOR.227, 148/33.2, 257/E21.546
• US Class Current: 438/222
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into the wafer. A shallow trench isolation (STI) layer is formed in the opening in the silicon nitride and in the trench in the wafer which will, under certain conditions, form with an undesirable void. The silicon nitride and pad oxide layers are removed, then an epitaxial silicon layer is formed on the silicon wafer between the STI. A gate/tunnel oxide layer is formed on the epitaxial silicon layer, then a word line is formed over the gate/tunnel oxide. The epitaxial silicon layer ensures that some minimum distance is maintained between the gate/tunnel oxide and the void in the STI. Wafer processing may then be continued to form a completed semiconductor device.

Claims

1. A method for use during fabrication of a semiconductor device, comprising:

providing a semiconductor wafer substrate assembly comprising at least a portion of a semiconductor wafer;

forming a vertical spacing layer over the semiconductor wafer substrate assembly;

etching at least one opening through the vertical spacing layer and at least partially into the semiconductor wafer substrate assembly;

forming a trench isolation layer within the opening through the vertical spacing layer and within the opening in the semiconductor wafer substrate assembly, wherein the trench isolation layer comprises a void therein at a location within the opening in the semiconductor wafer substrate assembly;

removing the vertical spacing layer such that the trench isolation layer comprises a portion which protrudes from a surface of the semiconductor wafer substrate assembly;

forming an epitaxial layer over the semiconductor wafer substrate assembly which is laterally located from the trench isolation layer;

forming a gate dielectric layer over the epitaxial layer; and

forming a transistor gate over the gate dielectric layer.

2. The method of claim 1 further comprising forming the epitaxial layer having an upper surface, wherein the upper surface of the epitaxial layer is closer to the at least a portion of the semiconductor wafer than an upper surface of the trench isolation layer.

3. The method of claim 1 further comprising forming the epitaxial layer having an upper surface, wherein the upper surface of the epitaxial layer is about the same distance from the at least a portion of the semiconductor wafer as an upper surface of the trench isolation layer.

4. The method of claim 1 wherein a first distance from the void in the trench isolation layer to a bottom surface of the epitaxial layer is less than a second distance from the void in the trench isolation layer to the gate dielectric layer.

5. The method of claim 1 further comprising forming the epitaxial layer to have a rounded or conical profile.

6. The method of claim 1 further comprising etching the at least one opening through the vertical spacing layer and at least partially into the semiconductor wafer substrate assembly to have a width less than about 50 nanometers and an aspect ratio of at least 4:

1.

7. The method of claim 1 further comprising forming the vertical spacing layer to a thickness of between about 250 angstroms and about 1,000 angstroms.

8. A method for use during fabrication of a semiconductor device, comprising:

providing a semiconductor wafer substrate assembly comprising a semiconductor wafer;

forming a vertical spacing layer over the semiconductor wafer;

etching through the vertical spacing layer and at least partially into the semiconductor wafer to form at least first and second openings through the vertical spacing layer and at least first and second laterally spaced openings in the semiconductor wafer;

forming a trench isolation layer in the at least first and second openings through the vertical spacing layer and into the at least first and second laterally spaced openings in the semiconductor wafer, wherein the trench isolation layer comprises at least one void within each of the at least first and second laterally spaced openings in the semiconductor wafer;

removing the vertical spacing layer to expose the semiconductor wafer and to result in the trench isolation layer within the first and second laterally spaced openings in the semiconductor wafer protruding from a surface of the semiconductor wafer;

forming an epitaxial layer on the semiconductor wafer at a location between the trench isolation layer in the first and second openings; and

forming at least first, second, and third transistors, wherein the first transistor at least partially overlies the trench isolation layer within the first opening in the semiconductor wafer, the second transistor at least partially overlies the trench isolation layer within the second opening in the semiconductor wafer, and the third transistor overlies the epitaxial layer between the trench isolation in the first and second openings overlies neither the trench isolation layer within the first nor the second opening in the semiconductor wafer.

9. The method of claim 8 further comprising forming a gate dielectric layer over the epitaxial layer between trench isolation layer in the first and second openings, wherein a first distance from a top of each void in the trench isolation layer in each of the first and second openings in the semiconductor wafer to a bottom surface of the epitaxial layer is less than a second distance from the top of each void to a bottom of the gate dielectric layer.

10. The method of claim 8 further comprising forming the vertical spacing layer to a thickness of between about 250 angstroms and about 1,000 angstroms.

11. The method of claim 8 further comprising forming the vertical spacing layer to a thickness of about 1,000 angstroms.

12. A semiconductor device comprising:

a semiconductor wafer section having an opening therein;

an epitaxial layer having an opening therein congruent with the opening in the semiconductor wafer section and comprising a conductively doped region which provides a transistor channel;

a trench isolation layer within the opening in the semiconductor wafer section and within the opening in the epitaxial layer, the trench isolation layer comprising a void therein;

a transistor gate dielectric layer on the epitaxial layer; and

a transistor gate on the gate dielectric layer.

13. The semiconductor device of claim 12 further comprising:

a major surface of the semiconductor wafer section; and

a bottom surface of the gate dielectric layer,

wherein the void in the trench isolation layer is closer to the major surface of the semiconductor wafer section than to the bottom surface of the gate dielectric layer.

14. The semiconductor device of claim 12 wherein the epitaxial layer exhibits a conical or rounded profile.