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Method and structure for shallow trench isolation during integrated circuit device manufacture

  • US 7,279,377 B2
  • Filed: 08/10/2005
  • Issued: 10/09/2007
  • Est. Priority Date: 08/10/2005
  • Status: Active Grant
First Claim
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1. A method for use during fabrication of a semiconductor device, comprising:

  • providing a semiconductor wafer substrate assembly comprising at least a portion of a semiconductor wafer;

    forming a vertical spacing layer over the semiconductor wafer substrate assembly;

    etching at least one opening through the vertical spacing layer and at least partially into the semiconductor wafer substrate assembly;

    forming a trench isolation layer within the opening through the vertical spacing layer and within the opening in the semiconductor wafer substrate assembly, wherein the trench isolation layer comprises a void therein at a location within the opening in the semiconductor wafer substrate assembly;

    removing the vertical spacing layer such that the trench isolation layer comprises a portion which protrudes from a surface of the semiconductor wafer substrate assembly;

    forming an epitaxial layer over the semiconductor wafer substrate assembly which is laterally located from the trench isolation layer;

    forming a gate dielectric layer over the epitaxial layer; and

    forming a transistor gate over the gate dielectric layer.

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