Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions

• US 7,279,701 B2
• Filed: 09/14/2004
• Issued: 10/09/2007
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Kreps, Scott A.
• Primary Examiner(s): Pham; Long
• Application Number:
  US10/941,062
• Publication Number:
  US 20050110003A1
• Time in Patent Office: 1,120 Days
• Field of Search: 257/28, 257/20, 257/288
• US Class Current: 257/28
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The MOSFET may include spaced apart source and drain regions on the semiconductor substrate, and a superlattice including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. The superlattice may have upper portions extending above adjacent upper portions of the source and drain regions, and lower portions contacting the source and drain regions so that a channel is defined in lower portions of said superlattice. Furthermore, each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. A gate may overly the superlattice.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) comprising

spaced apart source and drain regions on said semiconductor substrate,

a superlattice comprising a plurality of stacked groups of layers on said semiconductor substrate between said source and drain regions, said superlattice having upper portions extending above adjacent upper portions of said source and drain regions and lower portions contacting said source and drain regions so that a channel is defined in lower portions of said superlattice,

each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon,

said at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and

a gate overlying said superlattice.

2. The semiconductor device of claim 1 wherein each of said source and drain regions comprises a respective epitaxial silicon layer.

3. The semiconductor device of claim 2 wherein said superlattice has a greater thickness than said epitaxial silicon layers.

4. The semiconductor device of claim 1 wherein said source and drain regions each have a respective trench therein adjacent said superlattice;

and wherein the upper portions of said superlattice extend above bottom portions of the trenches.

5. The semiconductor device of claim 1 wherein said gate comprises an oxide layer overlying said superlattice channel and a gate electrode overlying said oxide layer.

6. The semiconductor device of claim 1 further comprising a contact layer on at least one of said source and drain regions.

7. The semiconductor device of claim 1 wherein said superlattice has a common energy band structure therein.

8. The semiconductor device of claim 1 wherein said superlattice has a higher charge carrier mobility than would otherwise be present without said non-semiconductor layer.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

10. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

11. The semiconductor device of claim 1 wherein each non-semiconductor monolayer compises oxygen.

12. The semiconductor device of claim 1 wherein each non-semiconductor monolayer is a single monolayer thick.

13. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

14. The semiconductor device of claim 1 wherein said superlattice further has a substantially direct energy bandgap.

15. The semiconductor device of claim 1 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

16. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

17. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

18. The semiconductor device of claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

19. A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) comprising

spaced apart source and drain regions on said semiconductor substrate,

a superlattice comprising a plurality of stacked groups of layers on said semiconductor substrate between said source and drain regions,

said source and drain regions each having a respective trench therein adjacent said superlattice, and said superiattice having upper portions extending above bottom portions of the trenches, and lower portions contacting said source and drain regions so that a channel is defined in lower portions of said superlattice,

each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

said energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and

a gate overlying said superlattice comprising an oxide layer overlying said superlattice channel and a gate electrode overlying said oxide layer.

20. The semiconductor device of claim 19 further comprising a contact layer on at least one of said source and drain regions.

21. The semiconductor device of claim 19 wherein said superlattice has a common energy band structure therein.

22. The semiconductor device of claim 19 wherein said superiattice has a higher charge carrier mobility than would otherwise be present without said non-semiconductor layer.

23. The semiconductor device of claim 19 wherein each base semiconductor portion comprises silicon.

24. The semiconductor device of claim 19 wherein each base semiconductor portion comprises germanium.

25. The semiconductor device of claim 19 wherein each energy band-modifying layer comprises oxygen.

26. The semiconductor device of claim 19 wherein each energy band-modifying layer is a single monolayer thick.

27. The semiconductor device of claim 19 wherein each base semiconductor portion is less than eight monolayers thick.

28. The semiconductor device of claim 19 wherein said superlattice further has a substantially direct energy bandgap.

29. The semiconductor device of claim 19 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

30. The semiconductor device of claim 19 wherein all of said base semiconductor portions are a same number of monolayers thick.

31. The semiconductor device of claim 19 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

32. The semiconductor device of claim 19 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

33. A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) comprising

spaced apart source and drain regions on said semiconductor substrate each comprising a respective epitaxial silicon layer,

a superlattice comprising a plurality of stacked groups of layers on said semiconductor substrate between said epitaxial silicon layers, said superlattice having a greater thickness than said epitaxial silicon layers, and lower portions of said superlattice contacting said epitaxial silicon layers so that a channel is defined in lower portions of said superlattice,

each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy bandmodifying layer thereon,

said energy-band modifying layer comprising at least one nonsemiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and

a gate overlying said superlattice comprising an oxide layer overlying said superlattice channel and a gate electrode overlying said oxide layer.

34. The semiconductor device of claim 33 further comprising a contact layer on at least one of said source and drain regions.

35. The semiconductor device of claim 33 wherein said superlattice has a common energy band structure therein.

36. The semiconductor device of claim 33 wherein said superlattice has a higher charge carrier mobility than would otherwise be present without said non-semiconductor layer.

37. The semiconductor device of claim 33 wherein each base semiconductor portion comprises silicon.

38. The semiconductor device of claim 33 wherein each base semiconductor portion comprises germanium.

39. The semiconductor device of claim 33 wherein each energy band-modifying layer comprises oxygen.

40. The semiconductor device of claim 33 wherein each energy band-modifying layer is a single monolayer thick.

41. The semiconductor device of claim 33 wherein each base semiconductor portion is less than eight monolayers thick.

42. The semiconductor device of claim 33 wherein said superlattice further has a substantially direct energy bandgap.

43. The semiconductor device of claim 33 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

44. The semiconductor device of claim 33 wherein all of said base semiconductor portions are a same number of monolayers thick.

45. The semiconductor device of claim 33 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

46. The semiconductor device of claim 33 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.