Circuit and method for processing a supply voltage with voltage peaks

• US 7,279,872 B2
• Filed: 02/27/2006
• Issued: 10/09/2007
• Est. Priority Date: 08/27/2003
• Status: Expired due to Fees

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Hohe, Hans-Peter, Hackner, Michael, Ernst, Roland
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US11/363,538
• Publication Number:
  US 20060181246A1
• Time in Patent Office: 589 Days
• Field of Search: 323/266, 323/273, 323/275, 323/303
• US Class Current: 323/275
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

A circuit for processing a supply voltage with a voltage peak to obtain an output signal with reduced or eliminated voltage peak, comprises a first capacitance and a second capacitance, wherein a controllable resistor is formed between the first and second capacitance in series to the same, which has a high resistance when a voltage at the first capacitance is smaller than an input voltage set value, and whose resistance is reduced to a lower resistance when the input voltage at the first capacitance is higher than or equal to the input voltage set value, so that finally, when the output voltage at the second capacitance reaches an output voltage set value, the controllable resistor is substantially no longer visible, but connects the two capacitances in parallel. The circuit is particularly advantageous as filter capacitance in a switching regulator, to achieve fast starting up of the switching regulator on the one hand and, on the other hand, simultaneously, fast charging of the second capacitance, wherein the energy of the voltage peak is used for charging the second capacitor more quickly.

Claims

1. A circuit for processing a supply voltage with a voltage peak to obtain an output voltage with reduced or eliminated voltage peaks, comprising:

a first capacitance between a first node and a second node, wherein an input voltage can be generated between the first node and the second node due to the supply voltage;

a second capacitance between a third node and a fourth node, wherein the output voltage can be tapped between the third node and the fourth node, wherein the first capacitance has a smaller capacitance value than the second capacitance;

a controllable resistor between the first node and the third node; and

a control device for controlling the controllable resistor, wherein the control device is formed

to control the controllable resistor in a first case, where the input voltage is smaller than a predetermined input voltage set value, such that the controllable resistor has a first high resistance,

to control the controllable resistor in a second case, where the input voltage is equal to or higher than the predetermined input voltage set value, and where the output voltage is smaller than a predetermined output voltage set value such that the controllable resistor has a second, lower resistance, so that a charge acceptance of the first capacitance is at least reduced and more charge flows into the second capacitance than in the case where the controllable resistor has the high resistance, and

to control the controllable resistor in a third case, where the output voltage at the second capacitance is equal to or higher than the predetermined output voltage set value, such that the same has a third low resistance so that the first capacitance and the second capacitance are substantially connected in parallel,

wherein the first resistance is higher than the second resistance, and

wherein the second resistance is higher than the third resistance.

2. The circuit according to claim 1, wherein the first resistance substantially represents an open and the third resistance substantially represents a short.

3. The circuit according to claim 1, wherein the control device is formed to reduce, in the second case, the second resistance monotonously falling from the first resistance to the third resistance.

4. The circuit according to claim 1, wherein the control device is formed to reduce, in the second case, the second resistance monotonously falling such that the input voltage does not move out of a tolerance range extending around the predetermined input voltage set value.

5. The circuit according to claim 4, wherein the tolerance range is chosen such that the same extends plus or minus 20% around the predetermined input voltage set value.

6. The circuit according to claim 1, wherein the first capacitance is dimensioned such that it is smaller than a limiting capacitance, which determines an upper limit for a time period how quickly the input voltage reaches the predetermined input voltage set value, when a supply voltage with a predetermined rising steepness is assumed.

7. The circuit according to claim 1, wherein the first capacitance is dimensioned such that it has a capacitance, which is at least so high that a predetermined amount of charge is stored on the first capacitance at the predetermined input voltage set value.

8. The circuit according to claim 7, wherein the predetermined amount of charge is so high that the control device for controlling the resistance or a control for regulating the input voltage is operable through the input voltage.

9. The circuit according to claim 1, wherein the second capacitance is at least so high that it can store a charge, which is driven into the first node due to a voltage peak of the supply voltage, without the output voltage generating a tolerance range around the predetermined output voltage set value.

10. The circuit according to claim 9, wherein the tolerance range extends to plus minus 20% around the predetermined output voltage set value.

11. The circuit according to claim 1, wherein the predetermined output voltage set value is equal to the predetermined input voltage set value.

12. The circuit according to claim 1, wherein the predetermined input and output set values are stored in the control device, and wherein the control device is formed to compare the input voltage to the stored predetermined input voltage set value and to compare the output voltage to the stored predetermined output voltage set value, for determining whether the first, second or third case is present.

13. The circuit according to claim 1, wherein the control device is formed to transit from the first case to the second case at one time based on a time state sequence, and to transit from the second case to the third case at a later time, wherein a time period between the second time and the first time is programmed into the control device.

14. A method for processing a supply voltage with a voltage peak for obtaining an output voltage with reduced or eliminated voltage peaks, comprising the steps of:

charging a first capacitance between a first node and a second node, wherein an input voltage is generated between the first node and the second node due to the supply voltage;

charging a second capacitance between a third node and a fourth node, wherein the output voltage is generated between the third node and the fourth node, wherein the first capacitance has a smaller capacitance value than the second capacitance;

controlling a resistor between the first node and the third node, such

that in a first case, where the input voltage is smaller than a predetermined input voltage set value, the controllable resistor has a first high resistance,

that in a second case, where the input voltage is equal to or higher than the predetermined input voltage set value, and where the output voltage is smaller than a predetermined output voltage set values, the controllable resistor has a second lower resistance, so that charging the first capacitance is at least reduced, and that charging the second capacitance is increased compared to the case where the controllable resistor has the high resistance, and

that in a third case, where the output voltage at the second capacitor is equal to or higher than the predetermined output voltage set value, the controllable resistor has a third lower resistance, so that the first capacitance and the second capacitance are substantially connected in parallel,

wherein the first resistance is higher than the second resistance, and

wherein the second resistance is higher than the third resistance.

15. A switching regulator for generating a regulated switching regulator output voltage by using an input voltage, comprising:

a controllable switch;

a network with a diode, an inductance and a filter device;

a switching regulator control for regulating the output voltage by periodically operating the controllable switch to regulate the output voltage, and

wherein the filter device comprises a circuit for processing a supply voltage with a voltage peak to obtain an output voltage with reduced or eliminated voltage peaks, comprising;

a first capacitance between a first node and a second node, wherein an input voltage can be generated between the first node and the second node due to the supply voltage;

a second capacitance between a third node and a fourth node, wherein the output voltage can be tapped between the third node and the fourth node, wherein the first capacitance has a smaller capacitance value than the second capacitance;

a controllable resistor between the first node and the third node; and

a control device for controlling the controllable resistor, wherein the control device is formed

to control the controllable resistor in a first case, where the input voltage is smaller than a predetermined input voltage set value, such that the controllable resistor has a first high resistance,

to control the controllable resistor in a second case, where the input voltage is equal to or higher than the predetermined input voltage set value, and where the output voltage is smaller than a predetermined output voltage set value such that the controllable resistor has a second, lower resistance, so that a charge acceptance of the first capacitance is at least reduced and more charge flows into the second capacitance than in the case where the controllable resistor has the high resistance, and

to control the controllable resistor in a third case, where the output voltage at the second capacitance is equal to or higher than a predetermined output voltage set value, such that the same has a third low resistance so that the first capacitance and the second capacitance are substantially connected in parallel,

wherein the first resistance is higher than the second resistance, and wherein the second resistance is higher than the third resistance.

16. The switching regulator according to claim 15, wherein the supply voltage can be provided to the first capacitance from a supply voltage generator, wherein the supply voltage generator comprises the coil and the diode of the network, and wherein the voltage at the second capacitor represents the output voltage of the switching regulator.

17. The switching regulator according to claim 15, wherein the switching regulator control is formed to control the controllable switch based on the input voltage at the first capacitance after switching on the switching regulator input voltage.

18. The switching regulator according to claim 15, wherein the switching regulator control device can be supplied by the input voltage at the first capacitance.

19. The switching regulator according to claim 15, wherein the switching regulator control is formed to control a change-over switch, wherein the change-over switch is connected to a voltage coupling device to either couple a potential at a positive output rail or a potential at a negative output rail to a control input of the controllable switch,

wherein the controllable switch is formed as transistor, and

wherein the control input of the controllable switch is a gate of the transistor.