Expeditious and low cost testing of RFID ICs
First Claim
1. A method for testing on-wafer integrated circuits (ICs), wherein each on-wafer IC contains an antenna and a memory, the method comprising:
- transmitting a first instruction and a first set of data to the on-wafer ICs, wherein the first instruction commands the on-wafer ICs to store the first set of data into the memory;
transmitting a second instruction and a second set of data to the on-wafer ICs, wherein the first set of data and the second set of data are the same, andwherein the second instruction commands the on-wafer ICs to compare the second set of data with the first set of data stored in the memory;
reading out results of the comparisons; and
marking a status of each on-wafer IC based on the result of the comparison associated with the on-wafer IC being marked wherein the marking comprises marking the on-wafer IC defective if the comparison indicates that the first set of data differs from the second set of data.
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Accused Products
Abstract
System and method for integrated circuit manufacturing. A preferred embodiment comprises transmitting a first set of data to integrated circuits (ICs) while they are in an on-wafer state and having each IC store the first set of data into memory, transmitting a second set of data to the ICs and having the ICs compare the second set of data with the first set of data stored in the memory, reading out the results of the comparisons, and marking an IC as being defective if the comparison indicates that that the first set of data did not match the second set of data. Each IC features an antenna formed in the scribe line region adjacent to the IC so that communications can take place while the IC remains on the wafer without the need to use electrical probes.
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Citations
15 Claims
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1. A method for testing on-wafer integrated circuits (ICs), wherein each on-wafer IC contains an antenna and a memory, the method comprising:
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transmitting a first instruction and a first set of data to the on-wafer ICs, wherein the first instruction commands the on-wafer ICs to store the first set of data into the memory; transmitting a second instruction and a second set of data to the on-wafer ICs, wherein the first set of data and the second set of data are the same, and wherein the second instruction commands the on-wafer ICs to compare the second set of data with the first set of data stored in the memory; reading out results of the comparisons; and marking a status of each on-wafer IC based on the result of the comparison associated with the on-wafer IC being marked wherein the marking comprises marking the on-wafer IC defective if the comparison indicates that the first set of data differs from the second set of data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for testing on-wafer integrated circuits (ICs), wherein each on-wafer IC contains an antenna and a memory, the method comprising:
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transmitting a first instruction and a set of data to the on-wafer ICs, wherein the first instruction commands the on-wafer ICs to store the set of data into memory; transmitting a transmit command to the on-wafer ICs; receiving the set of data from each on-wafer IC; comparing the set of data from each on-wafer IC with a copy of the set of data; and marking a status of each on-wafer IC based on the result of the comparison wherein an on-wafer IC is marked defective if the comparison of the set of data from the on-wafer IC and the copy of the set of data does not match, the method further comprising after the marking, cutting out the on-wafer ICs and discard the on-wafer ICs with a defective status. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification