Apparatus for delivering inputted signal data

• US 7,279,934 B2
• Filed: 12/22/2004
• Issued: 10/09/2007
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Do, Chang-Ho
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): Crawford; Jason
• Application Number:
  US11/017,672
• Publication Number:
  US 20060022706A1
• Time in Patent Office: 1,021 Days
• Field of Search: 326/68, 326 82- 83, 326 86- 87, 327/50, 327 52- 53, 327 77- 78, 327/89
• US Class Current: 326/83
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

An apparatus for receiving an inputted signal in order to transmit the inputted signal from an external circuit to an internal circuit includes a comparing block, enabled by an enable signal, for outputting a logic value to the internal circuit in response to a voltage difference between the inputted signal and a reference voltage; a biasing block for biasing the comparing block in order to sink a current from the comparing block to a ground; and a bias control block for receiving a fixed control signal and outputting the fixed control signal in response to the enable signal.

Claims

1. An apparatus for receiving an inputted signal in order to transmit the inputted signal from an external circuit to an internal circuit, comprising:

a comparing block, enabled by an enable signal, for comparing an inputted signal with a reference voltage to output a logic value corresponding to a logic level of the inputted signal to the internal circuit;

a biasing block for biasing the comparing block in order to sink a current from the comparing block to a ground;

a fixed voltage source, which produces a fixed voltage level between a supply and a ground, and

a bias control block for receiving the fixed voltage from the fixed voltage source and outputting the fixed voltage in response to the enable signal.

2. The apparatus as recited in claim 1, wherein the comparing block includes a differential amplifier for receiving the inputted signal at one side and the reference voltage at the other side to amplify the voltage difference between the inputted signal and the reference voltage.

3. The apparatus as recited in claim 2, wherein the comparing block further includes:

a first MOS transistor for activating one side of the differential amplifier in response to the enable signal; and

a second MOS transistor for activating the other side of the differential amplifier in response to the enable signal.

4. The apparatus as recited in claim 1, wherein the biasing block includes a first MOS transistor coupled between the comparing block and the ground for sinking a current flowed through the comparing block in response to the fixed voltage output by the bias control block.

5. The apparatus as recited in claim 4, wherein the bias control block includes:

a first inverter for inverting the enable signal;

a first transmission gate for transmitting the fixed voltage in response to the enable signal; and

a second MOS transistor for supplying the ground in order to turn off the first MOS transistor of the biasing block when the enable signal is inactivated.

6. The apparatus as recited in claim 1, further comprising a test bias control block for controlling the biasing block in a test mode.

7. The apparatus as recited in claim 6, wherein the biasing block includes:

a first MOS transistor coupled between the comparing block and the ground for sinking a current flowed through the comparing block in response to the fixed voltage output by the bias control block; and

a second MOS transistor coupled between the comparing block and the ground for sinking a current flowed through the comparing block in response to the enable signal during the test mode.

8. The apparatus as recited in claim 7, wherein the bias control block includes:

a first inverter for inverting the enable signal;

a first transmission gate for transmitting the fixed voltage in response to the enable signal; and

a third MOS transistor for supplying the ground in order to turn off the first MOS transistor of the biasing block when the enable signal is inactivated.

9. The apparatus as recited in claim 8, wherein the test bias control block includes:

a second inverter for inverting a test enable signal;

a second transmission gate for transmitting the enable signal in response to the test enable signal; and

a fourth MOS transistor for supplying the ground in order to turn off the second MOS transistor of the biasing block when the test enable signal is inactivated.