Digital frequency locked loop and phase locked loop frequency synthesizer

• US 7,279,988 B1
• Filed: 03/17/2005
• Issued: 10/09/2007
• Est. Priority Date: 03/17/2005
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Janesch, Stephen T., King, Eric J.
• Primary Examiner(s): Chang; Joseph
• Application Number:
  US11/082,277
• Time in Patent Office: 936 Days
• Field of Search: 331/10, 331/17
• US Class Current: 331/10
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A frequency synthesizer including frequency and phase locked loop that operates in either a frequency locked loop (FLL) mode or a phase locked loop (PLL) mode. In a first state, the frequency and phase locked loop operates in the FLL mode for initial frequency acquisition. Once the frequency and phase locked loop has locked in FLL mode, the frequency and phase locked loop transitions to the PLL mode for normal operation.

Claims

1. A frequency synthesizer comprising:

a frequency and phase locked loop adapted to receive a mode control signal and to operate in a frequency locked loop (FLL) mode when the mode control signal is in a first state and in a phase locked loop (PLL) mode when the mode control signal is in a second state, wherein the frequency and phase locked loop comprises;

a controlled oscillator adapted to provide an output frequency based on a control signal;

feed-back circuitry adapted to receive the output frequency and provide a feed-back phase;

first circuitry adapted to receive a reference frequency and the mode control signal and provide the reference frequency when the mode control signal is in the first state and provide a reference phase when the mode control signal is in the second state, wherein the reference phase is provided based on the reference frequency;

second circuitry adapted to receive the feed-back phase and the mode control signal and provide a feed-back frequency when the mode control signal is in the first state and provide the feed-back phase when the mode control signal is in the second state, wherein the feed-back frequency is provided based on the feed-back phase;

a frequency and phase detector adapted to receive either the reference frequency and the feed-back frequency or the reference phase and the feed-back phase and generate an error signal based on a difference between the reference frequency and the feed-back frequency or the reference phase and the feed-back phase; and

a loop filter adapted to receive the error signal and provide the control signal based on the error signal.

2. The frequency synthesizer of claim 1 wherein the frequency and phase locked loop is an all digital circuit.

3. The frequency synthesizer of claim 2 wherein the controlled oscillator is a digitally controlled oscillator.

4. The frequency synthesizer of claim 2 wherein the reference frequency is a digital control word.

5. The frequency synthesizer of claim 2 wherein the loop filter is a digital loop filter comprising at least one amplifier having a gain controlled by a gain control signal.

6. The frequency synthesizer of claim 5 further comprising a controller adapted to provide the gain control signal to the at least one amplifier in the digital loop filter, thereby controlling a bandwidth of the digital loop filter.

7. The frequency synthesizer of claim 2 wherein the first circuitry comprises:

a phase accumulator adapted to receive the reference frequency and provide the reference phase based on the reference frequency, wherein the reference frequency is a digital control word; and

multiplexing circuitry adapted to receive the reference frequency, the reference phase, and the mode control signal and provide the reference frequency when the mode control signal is in the first state and provide the reference phase when the mode control signal is in the second state.

8. The frequency synthesizer of claim 2 wherein the second circuitry comprises:

a phase-to-frequency converter adapted to receive the feed-back phase from the feed-back circuitry and provide the feed-back frequency based on the feed-back phase; and

multiplexing circuitry adapted to receive the feed-back frequency, the feed-back phase, and the mode control signal and provide the feed-back frequency when the mode control signal is in the first state and provide the feed-back phase when the mode control signal is in the second state.

9. The frequency synthesizer of claim 8 wherein the phase-to-frequency converter comprises:

a register adapted to receive a current value of the feed-back phase and provide a previous value of the feed-back phase; and

difference circuitry adapted to provide the feed-back frequency based on a difference between the current value of the feed-back phase and the previous value of the feed-back phase.

10. The frequency synthesizer of claim 2 wherein the feed-back circuitry comprises:

counter circuitry clocked by the output frequency; and

sampling circuitry adapted to sample an output signal from the counter circuitry and provide the feed-back phase.

11. A method generating a frequency comprising:

operating a frequency and phase locked loop adapted to operate in a frequency locked loop (FLL) mode or a phase locked loop (PLL) mode based on a mode control signal in the FLL mode when the mode control signal is in a first state; and

operating the frequency and phase locked loop in the PLL mode when the mode control signal is in a second state, further comprising;

generating an output frequency based on a control signal;

generating a feed-back phase based on the output frequency;

generating a feed-back frequency based on the feed-back phase;

receiving a reference frequency;

generating a reference phase based on the reference frequency;

providing the reference frequency and the feed-back frequency when the mode control signal is in the first state;

providing the reference phase and the feed-back phase when the mode control signal is in the second state;

generating an error signal based on a difference between either the reference frequency and the feed-back frequency or the reference phase and the feed-back phase;

filtering the error signal to provide the control signal.

12. The method of claim 11 wherein the reference frequency is a digital control word.