Communication driver
First Claim
1. A gigabit Ethernet controller, comprising:
- sixteen sets of digital-to-analog converters (DACs), wherein the sixteen sets of DACs are arranged in parallel, wherein each DAC within a set of DACs is configured to receive an input signal and to provide an output signal, wherein each of the sixteen sets of DACs comprises a corresponding replica current circuit and wherein each of the sixteen sets of DACs comprises;
N current sources arranged in parallel, wherein each of the N current sources includes a respective control input, and wherein the output signal provided by each DAC comprises a sum of outputs of the N current sources; and
M delay elements, wherein an input of a first one of the M delay elements receives the input signal, wherein an mth one of the M delay elements includes an input in communication with an m−
1th one of the M delay elements, wherein an output of one of the M delay elements controls a corresponding control input of one of the N current sources, and wherein a sum of each output signal from a respective one of the sixteen sets of DACs forms an accumulated output signal.
2 Assignments
0 Petitions
Accused Products
Abstract
An Ethernet controller includes a plurality of sets of digital-to-analog converters (DACs). Each DAC receives an input signal and provides an output signal. Each of the plurality of sets of DACs includes a plurality of sets of replica current circuits. Each DAC includes current sources. Each current source includes a respective control input. The output signal provided by each DAC includes a sum of outputs of the current sources. Each DAC also includes delay elements. An input of a first one of the delay elements receives the input signal. An mth one of the delay elements includes an input in communication with an m-1th one of the delay elements. An output of one of the delay elements controls a corresponding control input of one of the current sources. A sum of each output signal from a respective one of the plurality of sets of DACs forms an accumulated output signal.
98 Citations
175 Claims
-
1. A gigabit Ethernet controller, comprising:
sixteen sets of digital-to-analog converters (DACs), wherein the sixteen sets of DACs are arranged in parallel, wherein each DAC within a set of DACs is configured to receive an input signal and to provide an output signal, wherein each of the sixteen sets of DACs comprises a corresponding replica current circuit and wherein each of the sixteen sets of DACs comprises;
N current sources arranged in parallel, wherein each of the N current sources includes a respective control input, and wherein the output signal provided by each DAC comprises a sum of outputs of the N current sources; and
M delay elements, wherein an input of a first one of the M delay elements receives the input signal, wherein an mth one of the M delay elements includes an input in communication with an m−
1th one of the M delay elements,wherein an output of one of the M delay elements controls a corresponding control input of one of the N current sources, and wherein a sum of each output signal from a respective one of the sixteen sets of DACs forms an accumulated output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
20. A gigabit Ethernet controller, comprising:
sixteen sets of means for converting digital-to-analog signals, wherein the sixteen sets of digital-to-analog signal converting means are arranged in parallel, wherein each digital-to-analog signal converting means within a set of digital-to-analog signal converting means is configured to receive an input signal and to provide an output signal, wherein each of the sixteen sets of digital-to-analog signal converting means comprises a corresponding replica current means, and wherein each of the sixteen sets of digital-to-analog signal converting means comprises;
N means for generating current arranged in parallel, wherein each of the N current generating means includes a respective means for control inputting, and wherein the output signal provided by each digital-to-analog signal converting means comprises a sum of outputs of the N current generating means; and
M means for delaying signals, wherein a means for inputting of a first one of the M signal delaying means receives the input signal, wherein an mth one of the M signal delaying means includes means for inputting in communication with an m−
1th one of the M signal delaying means,wherein a means for outputting of one of the M signal delaying means controls a corresponding control inputting means of one of the N current generating means, and wherein a sum of each output signal from a respective one of the sixteen sets of digital-to-analog signal converting means forms an accumulated output signal. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
-
39. A gigabit Ethernet controller, comprising:
sixteen sets of transmitters, wherein the sixteen sets of transmitters are arranged in parallel, wherein each transmitter within a set of transmitters is configured to receive an input signal and to provide an output signal, wherein each of the sixteen sets of transmitters comprises a corresponding replica current circuit, and wherein each transmitter comprises;
N current sources arranged in parallel, wherein each of the N current sources includes a respective control input, and wherein the output signal provided by each transmitter comprises a sum of outputs of the N current sources; and
M delay elements, wherein an input of a first one of the M delay elements receives the input signal, wherein an mth one of the M delay elements includes an input in communication with an m−
1th one of the M delay elements,wherein an output of one of the M delay elements controls a corresponding control input of one of the N current sources, and wherein a sum of each output signal from a respective one of the sixteen sets of transmitters forms an accumulated output signal. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
-
58. A gigabit Ethernet controller, comprising:
sixteen sets of means for transmitting signals, wherein the sixteen sets of signal transmitting means are arranged in parallel, wherein each signal transmitting means within a set of signal transmitting means is configured to receive an input signal and to provide an output signal, wherein each of the sixteen sets of signal transmitting means comprises a corresponding replica current means, and wherein each signal transmitting means comprises;
N means for generating current arranged in parallel, wherein each of the N current generating means includes a respective means for control inputting, and wherein the output signal provided by each signal transmitting means comprises a sum of outputs of the N current generating means; and
M means for delaying signals, wherein a means for inputting of a first one of the M signal delaying means receives the input signal, wherein an mth one of the M signal delaying means includes means for inputting in communication with an m−
1th one of the M signal delaying means,wherein means for outputting of one of the M signal delaying means controls a corresponding control inputting means of one of the N current generating means, and wherein a sum of each output signal from a respective one of the sixteen sets of signal transmitting means forms an accumulated output signal. - View Dependent Claims (59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76)
-
77. A communication method, comprising the steps of:
-
a.) receiving sixteen input signals;
b.) providing sixteen transmit signal components in accordance with the sixteen input signals, wherein for each transmit signal component, step (b) comprises the steps of;
c.) supplying N sources of current;
d.) controlling the supply of current from each of the N sources of current;
e.) delaying current from M of the N sources of current, wherein an input of a first one of the M delaying steps receives an input signal, wherein an input of the mth one of the M delaying steps receives a signal from an m−
1th one of the M delaying steps, andwherein an output of one of the M delaying steps controls a corresponding one of the N sources of current; and
f.) summing the delayed currents;
g.) providing sixteen replica current signals in accordance with the sixteen input signals; and
h.) combining the sixteen transmit signal components to produce a multilevel output signal. - View Dependent Claims (78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90)
-
-
91. A communication circuit, comprising:
a plurality of sets of digital-to-analog converters (DACs), wherein the plurality of sets of DACs are arranged in parallel, wherein each DAC within a set of DACs is configured to receive an input signal and to provide an output signal, wherein each of the plurality of sets of DACs comprises a corresponding replica current circuit, and wherein each DAC comprises;
N current sources arranged in parallel, wherein each of the N current sources includes a respective control input, and wherein the output signal provided by each DAC comprises a sum of outputs of the N current sources; and
M delay elements, wherein an mth one of the M delay elements includes an input in communication with an m−
1th one of the M delay elements,wherein an output of one of the M delay elements controls a corresponding control input of one of the N current sources, wherein the input of a first one of the M delay elements receives the input signal, and wherein a sum of each output signal from a respective one of the plurality of sets of DACs forms an accumulated output signal. - View Dependent Claims (92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108)
-
109. A communication circuit, comprising:
a plurality of sets of digital-to-analog converter (DAC) means, wherein the plurality of sets of DAC means are arranged in parallel, wherein each DAC means within a set of DAC means is configured to receive an input signal and to provide an output signal, wherein each of the plurality of sets of DAC means comprises a corresponding replica current means, and wherein each DAC means comprises;
N current source means arranged in parallel, wherein each of the N current source means includes a respective means for control inputting, and wherein the output signal provided by each DAC means comprises a sum of outputs of the N current source means; and
M delay means, wherein an mth one of the M delay means includes a means for inputting in communication with an m−
1th one of the M delay means,wherein means for outputting of one of the M delay means controls a corresponding control inputting means of one of the N current source means, and wherein a sum of each output signal from a respective one of the plurality of sets of DAC means forms an accumulated output signal. - View Dependent Claims (110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126)
-
127. An Ethernet controller, comprising:
a plurality of sets of transmitters, wherein the plurality of sets of transmitters are arranged in parallel, wherein each transmitter within a set of transmitters is configured to receive an input signal and to provide an output signal, wherein each of the plurality of sets of transmitters comprises a corresponding replica current circuit, and wherein each transmitter comprises;
N current sources arranged in parallel, wherein each of the N current sources includes a respective control input, and wherein the output signal provided by each transmitter comprises a sum of outputs of the N current sources; and
M delay elements, wherein an mth one of the M delay elements includes an input in communication with an m−
1th one of the M delay elements,wherein an output of one of the M delay elements controls a corresponding control input of one of the N current sources, wherein an input of a first one of the M delay elements receives the input signal, and wherein a sum of each output signal from a respective one of the plurality of sets of transmitters forms an accumulated output signal. - View Dependent Claims (128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144)
-
145. An Ethernet controller, comprising:
a plurality of sets of transmitting means, wherein the plurality of sets of transmitting means are arranged in parallel, wherein each transmitting means within a set of transmitting means is configured to receive an input signal and to provide an output signal, wherein each of the plurality of sets of transmitting means comprises a corresponding replica current means, and wherein each transmitting means comprises;
N current source means arranged in parallel, wherein each of the N current source means includes a respective means for control inputting, and wherein the output signal provided by each transmitting means comprises a sum of outputs of the N current source means; and
M delay means, wherein an mth one of the M delay means includes a means for inputting in communication with an m−
1th one of the M delay means,wherein means for outputting of one of the M delay means controls a corresponding control inputting means of one of the N current source means, and wherein a sum of each output signal from a respective one of the plurality of sets of transmitting means forms a transmit signal. - View Dependent Claims (146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162)
-
163. A communication method, comprising the steps of:
-
a.) receiving K input signals;
b.) providing K corresponding transmit signal components in accordance with each of the K input signals, wherein for each transmit signal component, step (b) comprises the steps of;
b1.) supplying N sources of current;
b2.) controlling the supply of current from each of the N sources of current;
b3.) delaying current from M of the N sources of current, wherein an input of a first one of the M delaying steps receives an input signal, wherein an input of the mth one of the M delaying steps receives a signal from an m−
1th one of the M delaying steps, andwherein an output of one of the M delaying steps controls a corresponding one of the N sources of current; and
b4.) summing the delayed currents;
c.) providing K replica current signals in accordance with the K input signals; and
d.) combining the K corresponding transmit signal components to produce a multi-level output signal. - View Dependent Claims (164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175)
-
Specification