Display method, display apparatus and data write circuit utilized therefor

• US 7,280,103 B2
• Filed: 02/06/2004
• Issued: 10/09/2007
• Est. Priority Date: 02/07/2003
• Status: Active Grant

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Ikeda, Takashi, Mori, Yukio, Taoka, Mineki
• Primary Examiner(s): Shalwala; Bipin
• Assistant Examiner(s): Kovalick; Vincent E.
• Application Number:
  US10/772,279
• Publication Number:
  US 20040155847A1
• Time in Patent Office: 1,341 Days
• Field of Search: 345/87, 345/89, 345/90, 345/98, 345/99, 345/204, 345/213, 345/690, 345/205, 345/215
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2320/106 Determination of movement vectors or equivalent parameters within the image
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2081 with combination of amplitude modulation and time modulation space and time error diffusion G09G3/2066
• CPC Class Codes: G09G 3/28 using luminous gas-discharge panels, e.g. plasma panels
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A hold-type display apparatus is more likely to suffer the deterioration in the visibility of moving images due to the blur effect, compared to an impulse-type display apparatus. A single frame period is divided into a first period and a second period. Pixel data to be written to a pixel are written in a concentrated manner in the first period during a frame period. At this time, a write value for the pixel is set to twice a value of the image data in order not to lower the brightness of the images as a whole. However, only if the doubled value exceeds a range that can be displayed, the remaining pixel data are written in the second period. Thus, the change in display brightness approximates the impulse-type display apparatus, so that the visibility of moving images is improved.

Claims

1. A data write circuit, for driving a hold-type display apparatus, which includes means for writing in a first period n times a desired pixel value to be written to a pixel and writing zero in a second period and thereafter where a frame period corresponding to a frame is divided into n parts and each divided period is denoted by first to nth period;

n being an integer greater than or equal to 2.

2. A data write circuit according to claim 1, wherein, when a pixel value that is n times the desired pixel value exceeds a displayable range of the display apparatus, said writing means writes to the pixel an upper limit value of the range in the first period, and an excess part that remains unwritten is written to the pixel upon arrival of the second period and, thereafter, an excess part that cannot be written out in an ith period (2≦

i≦

n−

1) is written sequentially upon arrival of an (i+1)th period.

3. A data write circuit according to claim 1, including:

a counter which counts write clocks of n times a normal speed;

a memory control unit which reads out a pixel value from a frame memory based on an output from said counter;

an output value determining unit which determines whether the current period is one of first to nth periods, based on an output from said counter and which outputs a write value corresponding to the thus determined period; and

a plurality of switches which transmit the write values outputted from said output value determining unit to pixels corresponding thereto.

4. A data write circuit according to claim 3, further including a range compressing unit which compresses a range of the pixel, prior to determination by said output value determining unit.

5. A data write circuit according to claim 1, further including means for calculating a pixel value to be written to the pixel, at the time the pixel value is written in the first to nth periods, in a manner such that the pixel value is calculated after the frame is reconstructed by incorporating a motion compensation that corresponds to time shifts for the divided periods.

6. A data write circuit according to claim 5, further including means for judging, based on the reliability of the reconstructed frame, whether calculation of a pixel value utilizing the reconstructed frame is to be performed or not.

7. A data write circuit, for driving a hold-type display apparatus, which includes means for writing in an ith period (2≦

i<

n) n times a desired pixel value to be written to a pixel and writing zero in periods other than the ith period where a frame period corresponding to a frame is divided into n parts and each divided period is denoted by first to nth period;

n being an integer greater than or equal to 2.

8. A data write circuit according to claim 7, wherein, when a pixel value that is n times the desired pixel value exceeds a displayable range of the display apparatus, said writing means writes, in the ith period, an upper limit value of the range to the pixel and distributes an excess part that cannot be written out in a symmetrical manner with the ith period at a center, so that pixel values thus distributed before and after the ith period are written to the pixel.

9. A data write circuit according to claim 7, including:

a counter which counts write clocks of n times a normal speed;

a memory control unit which reads out a pixel value from a frame memory based on an output from said counter;

an output value determining unit which determines whether the current period is one of first to nth periods, based on an output from said counter and which outputs a write value corresponding to the thus determined period; and

a plurality of switches which transmit the write values outputted from said output value determining unit to pixels corresponding thereto.

10. A data write circuit according to claim 9, further including a range compressing unit which compresses a range of the pixel, prior to determination by said output value determining unit.

11. A data write circuit according to claim 7, further including means for calculating a pixel value to be written to the pixel, at the time the pixel value is written in the first to nth periods, in a manner such that the pixel value is calculated after the frame is reconstructed by incorporating a motion compensation that corresponds to time shifts for the divided periods.

12. A data write circuit according to claim 11, further including means for judging, based on the reliability of the reconstructed frame, whether calculation of a pixel value utilizing the reconstructed frame is to be performed or not.

13. A hold-type display apparatus, including:

a pixel array;

a data write circuit, for writing data to said pixel array in a row direction, which includes means for writing in a first period n times a desired pixel value to be written to a pixel and writing 0 (zero) in a second period and thereafter where a frame period is divided into n parts and each divided period is denoted by first to nth period (n being an integer greater than or equal to

     2); and

a scanning line drive circuit which scans said pixel array in a column direction.

14. A hold-type display apparatus, including:

a pixel array;

a data write circuit, for writing data to said pixel array in a row direction, which includes means for writing in an ith period (2≦

i<

n) n times a desired pixel value to be written to a pixel and writing zero in periods other than the ith period where a frame period is divided into n parts and each divided period is denoted by first to nth period;

n being an integer greater than or equal to 2; and

a scanning line drive circuit which scans said pixel array in a column direction.