API communications for vertex and pixel shaders

• US 7,280,111 B2
• Filed: 11/05/2004
• Issued: 10/09/2007
• Est. Priority Date: 03/07/2000
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Toelle, Michael A., Boyd, Charles F.
• Primary Examiner(s): Tung; Kee M.
• Assistant Examiner(s): Nguyen; Hau H
• Application Number:
  US10/981,963
• Publication Number:
  US 20050140669A1
• Time in Patent Office: 1,068 Days
• Field of Search: 345/559, 345/561, 345/538, 345/426, 345/522
• US Class Current: 345/559
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 2210/32 Image data format

Abstract

A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

Claims

1. A method, comprising:

providing a hardware rendering device having on-chip register storage;

communicating at least one instruction from a host computing system to said hardware rendering device, wherein said host computing system has a main memory and having stored thereon a 3-D API, and wherein said at least one instruction has at least one graphics data argument formatted for the register storage of said hardware rendering device;

receiving at least one instruction with said hardware rendering device;

processing with the hardware rendering device processes said at least one graphics data argument incident to the performance of said at least one instruction without accessing the main memory of the host computing system and said hardware rendering device outputs the result of the processing, wherein said at least one instruction is an instruction with at least one floating point number argument and said hardware rendering device outputs the fractional portion of said at least one floating point number; and

outputting with said hardware rendering device four fractional portions of corresponding four floating point number arguments.

2. The method of claim 1, wherein said at least one graphics data argument is formatted to be remapped to the register state of register storage.

3. The method of claim 1, wherein said at least one instruction is communicated directly to said hardware rendering device and the main memory stack of the host computing system is bypassed.

4. The method of claim 1, wherein incident to the processing of said at least one graphics data argument, the hardware rendering device performs at least one of reading from and writing to on-chip register storage.

5. The method of claim 1, wherein said hardware rendering device further comprises a register index stored in the on-chip register storage.

6. The method of claim 5, wherein the register index stored in the on-chip register storage is accessed pursuant to said at least one instruction and another register is located for use in connection with carrying out said at least one instruction.

7. The method of claim 1, wherein said hardware rendering device further includes a processor and an arithmetic/logic unit.

8. The method of claim 1, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said hardware rendering device processes the plurality of floating point number arguments to calculate a linear interpolation number representative of a linear interpolation between two of the floating point number arguments and wherein said hardware rendering device outputs said linear interpolation number.

9. The method of claim 1, wherein said at least one instruction includes a special modifier function to be performed during processing by the hardware rendering device.

10. The method of claim 9, wherein said special modifier function performed during said processing by the hardware rendering device is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

11. A computer-readable medium having computer-executable instructions, wherein the computer-executable instructions perform:

providing a hardware rendering device having on-chip register storage;

communicating at least one instruction from a host computing system to said hardware rendering device, wherein said host computing system has a main memory and having stored thereon a 3-D API, and wherein said at least one instruction has at least one graphics data argument formatted for the register storage of said hardware rendering device;

receiving at least one instruction with said hardware rendering device;

processing with the hardware rendering device processes said at least one graphics data argument incident to the performance of said at least one instruction without accessing the main memory of the host computing system and said hardware rendering device outputs the result of the processing, wherein said at least one instruction is an instruction with at least one floating point number argument and said hardware rendering device outputs the fractional portion of said at least one floating point number; and

outputting with said hardware rendering device four fractional portions of corresponding four floating point number arguments.

12. The computer-readable medium of claim 11, wherein said at least one graphics data argument is formatted to be remapped to the register state of register storage.

13. The computer-readable medium of claim 11, wherein said at least one instruction is communicated directly to said hardware rendering device and the main memory stack of the host computing system is bypassed.

14. The computer-readable medium of claim 11, wherein incident to the processing of said at least one graphics data argument, the hardware rendering device performs at least one of reading from and writing to on-chip register storage.

15. The computer-readable medium of claim 11, wherein said hardware rendering device further comprises a register index stored in the on-chip register storage.

16. The computer-readable medium of claim 15, wherein the register index stored in the on-chip register storage is accessed pursuant to said at least one instruction and another register is located for use in connection with carrying out said at least one instruction.

17. The computer-readable medium of claim 11, wherein said hardware rendering device further includes a processor and an arithmetic/logic unit.

18. The computer-readable medium of claim 11, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said hardware rendering device processes the plurality of floating point number arguments to calculate a linear interpolation number representative of a linear interpolation between two of the floating point number arguments and wherein said hardware rendering device outputs said linear interpolation number.

19. The computer-readable medium of claim 11, wherein said at least one instruction includes a special modifier function to be performed during processing by the hardware rendering device.

20. The computer-readable medium of claim 19, wherein said special modifier function performed during said processing by the hardware rendering device is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.