Integrated circuit device having input/output electrostatic discharge protection cell equipped with electrostatic discharge protection element and power clamp

• US 7,280,329 B2
• Filed: 08/27/2004
• Issued: 10/09/2007
• Est. Priority Date: 08/27/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Han-gu, Jang, Sung-pil, Lee, Ki-tae, Kim, Woo-sub, Ko, Jae-hyok
• Primary Examiner(s): Sherry; Michael
• Assistant Examiner(s): Benenson; Boris
• Application Number:
  US10/929,057
• Publication Number:
  US 20050045955A1
• Time in Patent Office: 1,138 Days
• Field of Search: 361/56, 361/111
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a V_DD ESD protection element connected between an I/O pad and a V_DD line, a ground voltage (V_SS) ESD protection element connected between the I/O pad and a V_SS line, and a power clamp element connected between the V_DD line and the V_SS line, and wherein the V_DD ESD protection element, the power clamp element, and the V_SS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

Claims

1. An integrated circuit device having an I/O ESD (input/output electrostatic discharge) protection cell, wherein the I/O ESD protection cell comprises:

a power supply voltage (V_DD) ESD protection element connected between an I/O pad and a V_DD line;

a ground voltage (V_SS) ESD protection element connected between the I/O pad and a V_SS line; and

a power clamp element connected between the V_DD line and the V_SS line, wherein the V_DD ESD protection element, the power clamp element, and the V_SS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

2. The integrated circuit device of claim 1, comprising a plurality of I/O pads, wherein the I/O ESD protection cell is provided for each of the I/O pads, and wherein the pitch and height of the I/O ESD protection cell is determined depending on the pitch and height of the I/O pad.

3. The integrated circuit device of claim 1, wherein the power clamp element is arranged between the V_DD ESD protection element and the V_SS ESD protection element.

4. The integrated circuit device of claim 1, wherein at least a portion of the I/O ESD protection cell is formed below the I/O pad.

5. The integrated circuit device of claim 1, wherein the I/O ESD protection cell is formed below the I/O pad.

6. The integrated circuit device of claim 1, wherein elements constituting the I/O ESD protection cell are comprised of at least one of diodes, MOS transistors, bipolar. transistors, field transistors, thyristors, and a combination thereof.