Semiconductor memory device
First Claim
1. A semiconductor memory device, comprising:
- a plurality of word lines;
a plurality of plate lines respectively provided adjacent to said word lines;
a plurality of bit lines provided in an orthogonal direction relative to said word lines and said plate lines;
a plurality of memory cells provided at intersection portions of sets of said word lines and said plate lines, with said bit lines, and respective having a ferroelectric capacitor; and
a plurality of clamp circuits respectively connected between said bit lines and nodes being supplied with reference potentials, andwherein each clamp circuit is a transistor whose ON resistance is larger than that of a transistor constituting said memory cell, in which a drain is connected to one of said plurality of bit lines, a source is connected to the node being supplied with the reference potential, and a gate is connected to a control signal line.
4 Assignments
0 Petitions
Accused Products
Abstract
In a semiconductor memory device including memory cells respective having a ferroelectric capacitor, and are provided at intersection portions of sets of a plurality of word lines and plate lines which is adjacent thereto, with bit lines, clamp circuits are respectively connected between the bit lines and nodes being supplied with reference potentials. Herewith, electric charges supplied from the ferroelectric capacitors to the bit lines are extracted by the clamp circuits, and capacities of the bit lines are increased artificially. Consequently, during a data read operation, an amount of electric potential change of the bit lines according to stored data in the ferroelectric capacitors is improved, and it becomes possible to obtain a large potential difference between the bit lines.
-
Citations
12 Claims
-
1. A semiconductor memory device, comprising:
-
a plurality of word lines; a plurality of plate lines respectively provided adjacent to said word lines; a plurality of bit lines provided in an orthogonal direction relative to said word lines and said plate lines; a plurality of memory cells provided at intersection portions of sets of said word lines and said plate lines, with said bit lines, and respective having a ferroelectric capacitor; and a plurality of clamp circuits respectively connected between said bit lines and nodes being supplied with reference potentials, and wherein each clamp circuit is a transistor whose ON resistance is larger than that of a transistor constituting said memory cell, in which a drain is connected to one of said plurality of bit lines, a source is connected to the node being supplied with the reference potential, and a gate is connected to a control signal line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A semiconductor memory device comprising:
-
a plurality of word lines; a plurality of plate lines respectively provided to adjacent to said word lines; a plurality of bit lines provided in an orthogonal direction relative to said word lines and said plate lines; a plurality of memory cells provided at intersection portions of sets of said word lines and said plate lines, with said bit lines, and respective having a ferroelectric capacitor; and a plurality of clamp circuits respectively connected between said bit lines and nodes being supplied with reference potentials wherein each clamp circuit has a switching function controlling whether between said bit line and the node being supplied with the reference potential is electrically connected or not, and wherein each clamp circuit has a transistor in which a drain is connected to one of said plurality of bit lines, and a gate is connected to the control signal line, and a resistor in which one end is connected to a source of the corresponding transistor and the other end is connected to the node being supplied with the reference potential.
-
Specification