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Semiconductor memory device

  • US 7,280,384 B2
  • Filed: 03/07/2005
  • Issued: 10/09/2007
  • Est. Priority Date: 02/27/2003
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device, comprising:

  • a plurality of word lines;

    a plurality of plate lines respectively provided adjacent to said word lines;

    a plurality of bit lines provided in an orthogonal direction relative to said word lines and said plate lines;

    a plurality of memory cells provided at intersection portions of sets of said word lines and said plate lines, with said bit lines, and respective having a ferroelectric capacitor; and

    a plurality of clamp circuits respectively connected between said bit lines and nodes being supplied with reference potentials, andwherein each clamp circuit is a transistor whose ON resistance is larger than that of a transistor constituting said memory cell, in which a drain is connected to one of said plurality of bit lines, a source is connected to the node being supplied with the reference potential, and a gate is connected to a control signal line.

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