System and memory for sequential multi-plane page memory operations

• US 7,280,398 B1
• Filed: 08/31/2006
• Issued: 10/09/2007
• Est. Priority Date: 08/31/2006
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, June
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US11/514,746
• Time in Patent Office: 404 Days
• Field of Search: 365/185.11, 365/185.33, 365/185.23, 365/185.05, 365/230.03
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array

Abstract

A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.

Claims

1. A flash memory receiving control signals, and command and address signals, the flash memory comprising:

an array of flash memory cells having a plurality of memory planes;

a state machine operable to generate memory control signals for executing memory operations for the plurality of memory planes in response to the control, command and address signals;

a plurality of memory plane control circuits, each control circuit associated with a respective one of the plurality of memory planes and coupled to the state machine to receive the memory control signals, each control circuit operable to control execution of memory operations for the respective memory plane in response to the control signals from the state machine when enabled by a respective active enable signal;

a plurality of data registers, each data register associated with a respective one of the plurality of memory planes; and

control circuit enable logic coupled to the state machine and coupled to the plurality of memory plane control circuits, the control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation for a first memory plane at a first time and initiate the memory operation for a second memory plane at a second time, the second time subsequent to the first time and during execution of the memory operation for the first memory plane.

2. The flash memory of claim 1 wherein the state machine comprises a state machine operable to generate memory control signals including control signals that repeat periodically to execute the memory operations.

3. The flash memory of claim 2 wherein the control circuit enable logic comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation in synchronicity with the periodically repeating control signals.

4. The flash memory of claim 1 wherein each of the memory plane control circuit includes a program driver operable to program data to memory cells of the respective memory plane.

5. The flash memory of claim 1 wherein the control circuit enable logic comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate at least one of a program operation, read operation, and erase operation.

6. A processor-based system, comprising:

a volatile memory operable to store data;

a processor coupled to the memory and operable to process data; and

a data storage coupled to the processor and operable to store data, the data storage including a flash memory receiving control signals, and command and address signals, the flash memory comprising;

an array of flash memory cells having a plurality of memory planes;

a state machine operable to generate memory control signals for executing memory operations for the plurality of memory planes in response to the control, command and address signals;

a plurality of memory plane control circuits, each control circuit associated with a respective one of the plurality of memory planes and coupled to the state machine to receive the memory control signals, each control circuit operable to control execution of memory operations for the respective memory plane in response to the control signals from the state machine when enabled by a respective active enable signal;

a plurality of data registers, each data register associated with a respective one of the plurality of memory planes; and

control circuit enable logic coupled to the state machine and coupled to the plurality of memory plane control circuits, the control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation for a first memory plane at a first time and initiate the memory operation for a second memory plane at a second time, the second time subsequent to the first time and during execution of the memory operation for the first memory plane.

7. The processor-based system of claim 6 wherein the state machine of the flash memory comprises a state machine operable to generate memory control signals including control signals that repeat periodically to execute the memory operations.

8. The processor-based system of claim 7 wherein the control circuit enable logic of the flash memory comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation in synchronicity with the periodically repeating control signals.

9. The processor-based system of claim 6 wherein each of the memory plane control circuits of the flash memory includes a program driver operable to program data to memory cells of the respective memory plane.

10. The processor-based system of claim 6 wherein the control circuit enable logic of the flash memory comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate at least one of a program operation, read operation, and erase operation.

11. A flash memory receiving control signals, and command and address signals, the flash memory comprising:

an array of flash memory cells having a plurality of memory planes;

a state machine operable to generate memory control signals for executing memory operations for the plurality of memory planes in response to the control, command and address signals;

a plurality of memory plane control circuits, each control circuit associated with a respective one of the plurality of memory planes and having a program driver operable to program data to memory cells of the respective memory plane, the plurality of control circuits coupled to the state machine to receive the memory control signals and operable to control execution of memory operations for the respective memory plane in response to the control signals from the state machine when enabled by a respective active enable signal; and

control circuit enable logic coupled to the state machine and coupled to the plurality of memory plane control circuits, the control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation for a first memory plane at a first time and initiate the memory operation for a second memory plane at a second time, the second time subsequent to the first time and during execution of the memory operation for the first memory plane.

12. The flash memory of claim 11 wherein the state machine comprises a state machine operable to generate memory control signals including control signals that repeat periodically to execute the memory operations.

13. The flash memory of claim 12 wherein the control circuit enable logic comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation in synchronicity with the periodically repeating control signals.

14. The flash memory of claim 11 wherein the control circuit enable logic comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate at least one of a program operation, read operation, and erase operation.

15. A processor-based system, comprising:

a volatile memory operable to store data;

a processor coupled to the memory and operable to process data; and

a data storage coupled to the processor and operable to store data, the data storage including a flash memory receiving control signals, and command and address signals, the flash memory comprising;

an array of flash memory cells having a plurality of memory planes;

a state machine operable to generate memory control signals for executing memory operations for the plurality of memory planes in response to the control, command and address signals;

a plurality of memory plane control circuits, each control circuit associated with a respective one of the plurality of memory planes and having a program driver operable to program data to memory cells of the respective memory plane, the plurality of control circuits coupled to the state machine to receive the memory control signals and operable to control execution of memory operations for the respective memory plane in response to the control signals from the state machine when enabled by a respective active enable signal; and

control circuit enable logic coupled to the state machine and coupled to the plurality of memory plane control circuits, the control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation for a first memory plane at a first time and initiate the memory operation for a second memory plane at a second time, the second time subsequent to the first time and during execution of the memory operation for the first memory plane.

16. The processor-based system of claim 15 wherein the state machine of the flash memory comprises a state machine operable to generate memory control signals including control signals that repeat periodically to execute the memory operations.

17. The processor-based system of claim 16 wherein the control circuit enable logic of the flash memory comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation in synchronicity with the periodically repeating control signals.

18. The processor-based system of claim 15 wherein the control circuit enable logic of the flash memory comprises control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate at least one of a program operation, read operation, and erase operation.