Non-volatile memory device with threshold voltage control function

• US 7,280,409 B2
• Filed: 03/17/2006
• Issued: 10/09/2007
• Est. Priority Date: 04/01/2005
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Misumi, Kenji, Kojima, Makoto
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US11/377,433
• Publication Number:
  US 20060221681A1
• Time in Patent Office: 571 Days
• Field of Search: 365/185.28, 365/185.29, 365/185.18
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

Even when the number of rewrite operations varies among erase unit areas, the number of rewrite operations is improved for all of the erase unit areas. A flash EEPROM 100 comprises a trimming value storing area 130 of storing a trimming value corresponding to each erase unit area 120 included in a memory cell array 110. When an erase operation and a write operation are performed with respect to a certain erase unit area 120, a regulator circuit 150 converts a voltage boosted by a booster circuit 140 to a level corresponding to the trimming value for the erase unit area 120. When a read determination circuit 170 detects an abnormality as the number of rewrite operations is increased, the trimming value is updated to a value which causes the regulator circuit 150 to increase the output voltage.

Claims

1. An electrically erasable and programmable non-volatile memory device comprising:

a plurality of erase unit areas each including a plurality of non-volatile memory cell transistors which are simultaneously selected in an erase operation;

a plurality of output regulating value storing sections provided corresponding to the respective erase unit areas, of storing output regulating values of the respective erase unit areas in a non-volatile manner;

a voltage generating circuit of generating a voltage having a level required in an erase operation and a write operation with respect to each of the erase unit areas;

a voltage regulating circuit of regulating the level of the voltage generated in the voltage generating circuit based on a corresponding one of the output regulating values provided thereto;

a read determination circuit of performing determination with respect to data after an erase operation and a write operation with respect to each of the erase unit areas; and

a control circuit of operating in an erase operation and a write operation with respect to each of the erase unit areas.

2. The non-volatile memory device according to claim 1, wherein the read determination circuit performs the determination step in accordance with a criterion stricter than when a read operation is performed.

3. The non-volatile memory device according to claim 2, wherein, when performing the determination step, the read determination circuit applies to a current detection type sense amplifier circuit a reference current which provides a criterion stricter than when a read operation is performed.

4. The non-volatile memory device according to claim 2, wherein when performing the determination step, the read determination circuit applies to the memory cell transistor a gate voltage which provides a criterion stricter than when a read operation is performed.

5. The non-volatile memory device according to claim 1, wherein the voltage regulating circuit includes a limiter circuit of limiting an output voltage within a breakdown-voltage specification of the memory cell transistor.

6. The non-volatile memory device according to claim 1, wherein the control circuit performs the steps of:

selecting one of the erase unit areas;

providing to the voltage regulating circuit the output regulating value stored in the output regulating value storing section corresponding to the selected erase unit area; and

performing a control so that, when the read determination circuit detects an abnormality as a result of the determination step after an erase operation and a write operation are performed with respect to the selected erase unit area, the output regulating value stored in the output regulating value storing section corresponding to the selected erase unit area is updated to a value which causes an output voltage to be higher than before, and thereafter, an erase operation and a write operation are performed again with respect to the selected erase unit area.

7. The non-volatile memory device according to 6, where, every time the output regulating value stored in the output regulating value storing section is updated, the control circuit performs a write operation after an erase operation with respect to the output regulating value storing section.

8. The non-volatile memory device according to claim 6, wherein, when the output regulating value stored in the output regulating value storing section is updated for the first time, the control circuit performs a write operation after an erase operation with respect to the output regulating value storing section, and when the output regulating value stored in the output regulating value storing section is updated for the second time and thereafter, the control circuit performs a write operation without an erase operation with respect to the output regulating value storing section.

9. The non-volatile memory device according to claim 8, wherein the voltage regulating circuit outputs voltages different from each other by a value selected in a range of 0.1 to 0.4 V, depending on the number of bits having a predetermined value in the provided output regulating value.

10. The non-volatile memory device according to claim 1, further comprising an output regulating value temporarily holding circuit of temporarily storing the output regulating value to be provided to the voltage regulating circuit.

11. The non-volatile memory device according to claim 10, wherein the control circuit performs the steps of:

selecting one of the erase unit areas;

providing to the voltage regulating circuit the output regulating value stored in the output regulating value storing section corresponding to the selected erase unit area;

performing a control so that, when the read determination circuit detects an abnormality as a result of the determination step after an erase operation and a write operation are performed with respect to the selected erase unit area, an output regulating value which causes an output voltage to be higher than before is set in the output regulating value temporarily holding circuit and the set output regulating value is provided to the voltage regulating circuit, and thereafter, an erase operation and a write operation are performed again with respect to the selected erase unit area; and

setting the output regulating value stored in the output regulating value temporarily holding circuit into the output regulating value storing section corresponding to the selected erase unit area after the erase operation and the write operation are normally performed with respect to the selected erase unit area.

12. The non-volatile memory device according to claim 10, further comprising an error flag circuit of temporarily storing a result of the determination step performed by the read determination circuit.

13. The non-volatile memory device according to claim 12, wherein the control circuit performs the steps of:

selecting one of the erase unit areas;

providing to the voltage regulating circuit the output regulating value stored in the output regulating value storing section corresponding to the selected erase unit area;

performing a control so that, when the read determination circuit detects an abnormality as a result of the determination step after an erase operation and a write operation are performed with respect to the selected erase unit area, an output regulating value which causes an output voltage to be higher than before is set in the output regulating value temporarily holding circuit and the set output regulating value is provided to the voltage regulating circuit, and thereafter, an erase operation and a write operation are performed again with respect to the selected erase unit area; and

setting the output regulating value stored in the output regulating value temporarily holding circuit into the output regulating value storing section corresponding to the selected erase unit area only when an abnormality is stored in the error flag circuit after the erase operation and the write operation are normally performed with respect to the selected erase unit area.

14. The non-volatile memory device of claim 1, further comprising a plurality of monitor bits provided corresponding to the respective erase unit areas and each composed of a memory cell transistor of the same type as that of the erase unit area,

wherein an erase operation is performed with respect to the monitor bit when an erase operation is performed with respect to the corresponding erase unit area, and a write operation is performed with respect to the monitor bit when a write operation is performed with respect to all or a portion of the memory cell transistors included in the corresponding erase unit area.

15. The non-volatile memory device according to claim 14, wherein the control circuit performs the steps of:

selecting one of the erase unit areas;

providing to the voltage regulating circuit the output regulating value stored in the output regulating value storing section corresponding to the selected erase unit area; and

performing a control so that, when the read determination circuit detects an abnormality as a result of the determination step after an erase operation and a write operation are performed with respect to the selected erase unit area, an output regulating value which causes an output voltage to be higher than before is provided to the voltage regulating circuit, and thereafter, an erase operation and a write operation are performed again with respect to the selected erase unit area,

wherein the read determination circuit performs the determination step with respect to the monitor bit corresponding to the selected erase unit area.

16. The non-volatile memory device according to claim 1, further comprising a data latch circuit of temporarily storing a plurality of output regulating values to be set in the output regulating value storing section.

17. The non-volatile memory device according to claim 16, wherein the control circuit performs the steps of:

selecting one of the erase unit areas;

providing to the voltage regulating circuit the output regulating value stored in the output regulating value storing section corresponding to the selected erase unit area;

performing a control so that, when the read determination circuit detects an abnormality as a result of the determination step after an erase operation and a write operation are performed with respect to the selected erase unit area, an output regulating value which causes an output voltage to be higher than before is provided to the voltage regulating circuit, and thereafter, an erase operation and a write operation are performed again with respect to the selected erase unit area;

setting into the data latch circuit the output regulating value provided to the voltage regulating circuit when an erase operation and a write operation have been normally performed with respect to the selected erase unit area; and

setting the plurality of output regulating values stored in the data latch circuit into the output regulating value storing section after an erase operation and a write operation are normally performed with respect to all of the erase unit areas.

18. The non-volatile memory device according to claim 1, further comprising a fixed output regulating value storing section of storing a fixed output regulating value to be provided to the voltage regulating circuit.

19. The non-volatile memory device according to claim 18, wherein the control circuit performs the steps of:

selecting one of the erase unit areas;

providing to the voltage regulating circuit the output regulating value stored in the output regulating value storing section corresponding to the selected erase unit area; and

performing a control so that, when the read determination circuit detects an abnormality as a result of the determination step after an erase operation and a write operation are performed with respect to the selected erase unit area, an output regulating value which causes an output voltage to be higher than before is provided to the voltage regulating circuit, and thereafter, an erase operation and a write operation are performed again with respect to the selected erase unit area,

wherein one of the erase operation and the write operation with respect to the erase unit area is performed while the output regulating value stored in the fixed output regulating value storing section is provided to the voltage regulating circuit.

20. The non-volatile memory device according to claim 19, wherein one of the erase operation and the write operation with respect to the erase unit area, the one having a smaller influence on a change in characteristics of the memory cell transistor, is performed while the output regulating value stored in the fixed output regulating value storing section is provided to the voltage regulating circuit.

21. The non-volatile memory device according to claim 15, wherein, when an erase operation and a write operation are performed with respect to the selected erase unit area for the first time, the control circuit updates the output regulating value to be provided to the voltage regulating circuit, depending on a result of the determination step with respect to all data included in the selected erase unit area, and when an erase operation and a write operation are performed with respect to the selected erase unit area for the second time and thereafter, the control circuit updates the output regulating value to be provided to the voltage regulating circuit, depending on a result of the determination step with respect to the monitor bit corresponding to the selected erase unit area.

22. The non-volatile memory device according to claim 21, wherein, when an erase operation and a write operation are performed with respect to the selected erase unit area for the second time and thereafter, an output regulating value when an erase operation and a write operation have been normally performed with respect to the selected erase unit area is provided to the voltage regulating circuit, and thereafter, an erase operation and a write operation are preformed again with respect to the selected erase unit area.

23. The non-volatile memory device according to claim 1, further comprising a busy circuit of outputting a busy signal indicating that an erase operation and a write operation are being performed with respect to one of the erase unit area and the output regulating value storing section.