Multi-column addressing mode memory system including an integrated circuit memory device

• US 7,280,428 B2
• Filed: 09/30/2004
• Issued: 10/09/2007
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Bellows, Chad A., Richardson, Wayne S., Lai, Lawrence, Ware, Frederick A.
• Primary Examiner(s): Lane; Jack
• Application Number:
  US10/955,193
• Publication Number:
  US 20060072366A1
• Time in Patent Office: 1,104 Days
• Field of Search: 711/5, 711/105, 711/154, 365/189.04, 365/230.03, 365/230.06
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.

Claims

1. An integrated circuit memory device, comprising:

an interface;

a storage array having a row of storage cells; and

a column decoder to access the row of storage cells, wherein the integrated circuit

memory device is operable in a first mode and second mode of operation,

wherein;

during the first mode of operation, the row of storage cells is accessible from the interface in response to a first column address; and

during the second mode of operation, a first plurality of storage cells in the row of storage cells is accessible from the interface in response to a second column address and a second plurality of storage cells in the row of storage cells is accessible from the interface in response to a third column address, wherein the first plurality of storage cells and the second plurality of storage cells are concurrently accessible from the interface.

2. The integrated circuit memory device of claim 1, wherein the first and second plurality of storage cells are accessible during a column cycle time interval.

3. The integrated circuit memory device of claim 1, wherein a first plurality of data is output from the first plurality of storage cells onto the interface during a first time interval and a second plurality of data is output onto the interface from the second plurality of storage cells during a second time interval.

4. The integrated circuit memory device of claim 1, wherein a first and second plurality of data is output from the first and second plurality of storage cells, respectively, onto the interface during a first time interval.

5. An integrated circuit memory device, comprising:

an interface;

a first storage array having a first row of storage cells;

a second storage array having a second row of storage cells;

a first column decoder to access the first row of storage cells; and

a second column decoder to access the second row of storage cells, wherein the integrated circuit memory device is operable in a first mode end a second mode, wherein;

during the first mode of operation, the first row of storage cells is accessible from the interface in response to a first column address; and

during the second mode of operation, a first and second plurality of data stored in the first and second row of storage cells, respectively, is accessible from the interface in response to a second and third column address, and a third and fourth plurality of data stored in the first and second row of storage cells, respectively, is accessible from the interface in response to a fourth and fifth column address, wherein the first plurality of data and the second plurality of data are concurrently provided at the interface, and wherein the third plurality of data and the fourth plurality of data are concurrently provided at the interface.

6. The integrated circuit memory device of claim 5, wherein the first and second plurality of data is provided at the interface during a first time interval, and the third and fourth plurality of data is provided at the interface during a second time interval.

7. The integrated circuit memory device of claim 6, wherein the interface is coupled to a first interconnect to transfer the first plurality of data and a second interconnect to transfer the second plurality of data.

8. An integrated circuit memory device, comprising:

an interface;

a first memory bank having a first row of storage cells;

a second memory bank having a second row of storage cells;

a third memory bank having a third row of storage cells;

a fourth memory bank having a fourth row of storage cells;

a first column decoder to access the first row of storage cells;

a second column decoder to access the second row of storage cells;

a third column decoder to access the third row of storage cells; and

a fourth column decoder to access the fourth row of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein;

during the first mode of operation, the first row of storage cells is accessible from the interface in response to a first column address; and

during the second mode of operation, a first and second plurality of data stored in the first and second row of storage cells, respectively, is accessible from the interface in response to a second and third column address, and a third and fourth plurality of data stored in the third and fourth row of storage cells, respectively, is accessible from the interface in response to a fourth and fifth column address.

9. The integrated circuit memory device of claim 8, wherein the first and second plurality of data is provided at the interface during a first time interval, and the third and fourth plurality of data is provided at the interface during a second time interval.

10. The integrated circuit memory device of claim 8, wherein the interface is coupled to a first interconnect to transfer the first and third plurality of data and a second interconnect to transfer the second and fourth plurality of data.

11. A memory system comprising:

a master device to provide a first, second and third column address; and

an integrated circuit memory device, including;

an interface coupled to the master device;

a first storage array having a first row of storage cells; and

a column decoder to access the first row of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein;

during the first mode of operation, the first row of storage cells is accessible from the interface in response to the first column address; and

during the second mode of operation. a first plurality of storage cells in the first row of storage cells is accessible from the interface in response to the second column address and a second plurality of storage cells in the first row of storage cells is accessible from the interface in response to the third column address.

12. The memory system of claim 11, wherein the second and third column addresses are transferred in a request packet by the master device.

13. The memory system of claim 11, wherein the first and second plurality of storage cells are accessible during a column cycle time interval.

14. The memory system of claim 11, wherein the master device is a graphics controller.

15. The memory system of claim 11, wherein the master device is a memory controller.

16. The memory system of claim 11, wherein the master device provides a fourth and fifth column address, and the integrated circuit memory device is operable in a third mode of operation, wherein:

during the third mode of operation, a first and second plurality of storage cells in the first row of storage cells is accessible at the interface in response to the second and third column address and a second and third plurality of storage cells in a second row of storage cells is accessible from the interface in response to a fourth and fifth column address.

17. The memory system of claim 16, wherein the second and third column addresses are transferred in a first request packet and the fourth and fifth column addresses are transferred in a second request packet by the master device.

18. The system of claim 16, wherein the master device is coupled to the integrated circuit memory device by a first and second external interconnect, wherein a first plurality of data is output from the first row in a first memory bank onto the first interconnect during a first time interval and a second plurality of data is output onto the second interconnect from the second row in a second memory bank during the first time interval.

19. A method comprising:

receiving a first column address to access a first plurality of storage cells in a row of storage cells during a first time interval; and

receiving a second column address to access a second plurality of storage cells in the row of storage cells during the first time interval.

20. The method of claim 19, wherein the first time interval is a column cycle time interval.

21. The meted of claim 19, further comprising:

generating the first column address by a master device; and

generating the second column address by the master device.

22. The method of claim 21, wherein the first and second column addresses are in a request packet.

23. A method comprising:

receiving a first column address to access a first plurality of storage cells in a first row of storage cells during a first time interval;

receiving a second column address to access a second plurality of storage cells in a second row of storage cells during the first time interval;

receiving a third column address to access a third plurality of storage cells in the first row during a second time interval; and

receiving a fourth column address to access a fourth plurality of storage cells in the second row of storage cells during the second time interval.

24. The method of claim 23, wherein the first and second time intervals are column cycle time intervals.

25. The method of claim 23, wherein the first row of storage cells is in a first memory bank and the second row of storage cells is in a second memory bank.

26. An integrated circuit memory device, comprising:

a storage array having a row of storage cells; and

means for accessing a first plurality of storage cells in the row in response to a first column address and accessing a second plurality of storage cells in the row, during a column cycle time interval, in response to a first and second column address.