Method and apparatus for non-speculative pre-fetch operation in data packet processing

• US 7,280,548 B2
• Filed: 04/06/2006
• Issued: 10/09/2007
• Est. Priority Date: 02/08/2000
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Sampath, Nandakumar, Musoll, Enrique, Melvin, Stephen, Nemirovsky, Mario
• Primary Examiner(s): MARCELO, MELVIN C
• Application Number:
  US11/278,890
• Publication Number:
  US 20060215670A1
• Time in Patent Office: 551 Days
• Field of Search: 370/401, 709/238, 712/207
• US Class Current: 370/401
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/56 Routing software
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/621 Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction
• CPC Class Codes: H04L 49/20 Support for services
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3036 Shared queuing
• CPC Class Codes: H04L 49/501 Overload detection
• CPC Class Codes: H04L 49/555 Error detection
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9073 : Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 69/12 : Protocol engines

Abstract

A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.

Claims

1. A system for processing packets, the system comprising:

a packet management unit (PMU) to;

select a context for processing a data packet;

identify a thread for use in processing the data packet;

convey an identification of the thread and the context; and

load information corresponding to the packet into the context; and

a processing unit to;

receive the identification of the thread and the context from the PMU; and

initiate a pre-fetch of instructions of the thread prior to the PMU completing the load of the information into the context.

2. The system of claim 1, wherein the packet management unit is identifies said thread by accessing a table which associates threads with packet types.

3. The system of claim 2, wherein said table comprises a plurality of queues, each of said queues for storing packets of a particular type.

4. The system of claim 3, wherein for each of said queues, the table comprises an identifier which identifies a thread for use in processing packets of a corresponding type.

5. The system of claim 4, wherein said identifier comprises an address of a first instruction of a thread.

6. The system of claim 2, wherein the table comprises a software configurable hardware table.

7. The system of claim 1, wherein said processing unit comprises a first portion for processing the data packets, and a second portion comprising a pool of context registers.

8. The system of claim 7, wherein said PMU selects said context from said pool of contexts via a dedicated link which couples the PMU to the processing unit.

9. The system of claim 1, wherein the processing unit pre-fetches one or more of said instructions at least partially in parallel with the PMU loading the information corresponding to the packet into the context.

10. The system of claim 3, wherein the PMU further en-queues a received data packet into one of said queues according to a classification scheme.

11. The system of claim 10, wherein the classification scheme is based on packet type and/or priority.

12. The system of claim 11, wherein said packet types include voice over Internet protocol packets and/or e-mail packets.

13. The system of claim 3, wherein in response to receiving a given packet of an undetermined type, the PMU stores the given packet in a special queue dedicated for storing unclassified packets, and convey an identification of a thread configured to identify packet types.

14. The system of claim 1, wherein said PMU and processing unit are part of a dynamic multi-streaming processor.

15. The system as recited in claim 1, wherein said pre-fetch is non-speculative.

16. A method for processing data packets, the method comprising:

selecting a context for processing a data packet;

identifying a thread for use in processing the data packet;

conveying an identification of the thread and the context;

loading information corresponding to the packet into the context; and

initiating a pre-fetch of instructions of the thread prior to completing said loading of the information into the context.

17. The method of claim 16, wherein said identifying comprises accessing a table which associates threads with packet types.

18. The method of claim 17, wherein said table comprises a plurality of queues, each of said queues being configured to store packets of a particular type.

19. The method of claim 18, wherein for each of said queues, the table comprises an identifier which identifies a thread for use in processing packets of a corresponding type.

20. The method of claim 19, wherein said identifier comprises an address of a first instruction of a thread.

21. The method of claim 17, wherein the table comprises a software configurable hardware table.

22. The method of claim 21, wherein said method comprises selecting said context from a pool of contexts.

23. The method of claim 16, wherein pre-fetching said instructions is performed at least partially in parallel with the loading of the information corresponding to the packet into the context.

24. The method of claim 18, further comprising en-queuing a received data packet into one of said queues according to a classification scheme.

25. The method of claim 24, wherein the classification scheme is based on packet type and/or priority.

26. The method of claim 25, wherein said packet types include voice over Internet protocol packets and/or e-mail packets.

27. The method of claim 18, wherein in response to receiving a given packet of an undetermined type, the method comprises storing the given packet in a special queue dedicated for storing unclassified packets, and conveying an identification of a thread configured to identify packet types.

28. The method of claim 16, wherein said pre-fetch is non-speculative.