Routing mechanisms in systems having multiple multi-processor clusters

• US 7,281,055 B2
• Filed: 05/28/2002
• Issued: 10/09/2007
• Est. Priority Date: 05/28/2002
• Status: Expired due to Fees

• Current Assignee: Sanmina-SCI Corporation
• Original Assignee: Newisys, Inc. (Sanmina-SCI Corporation)
• Inventors: Oehler, Richard R., Prasadh, Guru, Kota, Rajesh, Zeitler, Carl, Glasco, David Brian
• Primary Examiner(s): Avellino, Joseph E.
• Application Number:
  US10/156,893
• Publication Number:
  US 20030225938A1
• Time in Patent Office: 1,960 Days
• Field of Search: 709217-219, 709230-245, 709212-216, 370389-393, 712 10- 15, 711/150, 711147-148
• US Class Current: 709/232
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus

Abstract

A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.

Claims

1. A computer system comprising a plurality of processor clusters interconnected by a plurality of global point-to-point links and having a global memory address space associated therewith, each cluster including a plurality of local nodes and an interconnection controller interconnected by a plurality of local point-to-point links, each cluster having a local memory address space associated therewith corresponding to a first portion of the global memory address space, wherein the interconnection controller in each cluster is mapped by the associated local nodes to a remainder portion of the global memory address space exclusive of the first portion, each cluster having routing information associated with each of the local nodes for facilitating communication between the local nodes and the interconnection controller via specific ones of the local links identified in the associated routing information, wherein the interconnection controller in each cluster is operable to maintain at least one local routing table relating each of the local nodes to at least one of the local links, at least one global routing table relating each of the other clusters to at least one of the global links, and memory mapping information relating each of the other clusters to respective portions of the remainder portion of the global memory address space, and wherein the interconnection controller in each cluster is operable to map locally generated transmissions directed to the remainder portion of the global memory address space to the global links using the memory mapping information and the at least one global routing table, and remotely generated transmissions directed to the local nodes to the local links using the at least one local routing table.

2. The computer system of claim 1 wherein the at least one local routing table comprises a directed routing table for facilitating directed transmissions between specified nodes on the local links, and a broadcast routing table for facilitating broadcast transmission to more than one node on the local links.

3. The computer system of claim 1 wherein the at least one global routing table comprises a directed routing table for facilitating directed transmissions between specified nodes on the global links, and a broadcast routing table for facilitating broadcast transmission to more than one node on the global links.

4. The computer system of claim 1 wherein the local links comprise point-to-point links.

5. The computer system of claim 4 wherein the plurality of clusters comprises four clusters.

6. The computer system of claim 5 wherein the plurality of local nodes in each cluster comprises four local processors.

7. The computer system of claim 1 wherein the global links comprise point-to-point links.

8. The computer system of claim 1 wherein the interconnection controller in each cluster is further operable to uniquely map selected ones of locally generated transactions directed to others of the clusters to a global transaction space, and remotely generated transactions directed to the local nodes to a local transaction space.

9. The computer system of claim 1 wherein selected ones of the local nodes comprise various combinations of corresponding units including any of at least one central processing unit, at least one memory controller, and at least one input/output interface.

10. In a computer system comprising a plurality of processor clusters interconnected by a plurality of global point-to-point links and having a global memory address space associated therewith, each cluster including a plurality of local nodes and an interconnection controller interconnected by a plurality of local point-to-point links, each cluster having a local memory address space associated therewith corresponding to a first portion of the global memory address space, wherein the interconnection controller in each cluster is mapped by the associated local nodes to a remainder portion of the global memory address space exclusive of the first portion, a method for routing locally and remotely generated transmissions, the method comprising:

providing local routing information in each cluster, the local routing information including at least one local routing table maintained by the interconnection controller and relating each of the local nodes to at least one of the local links, a portion of the local routing information being associated with each of the local nodes for facilitating communication between the local nodes and the interconnection controller via specific ones of the local links identified in the portions of routing information;

providing global routing information in each cluster, the global routing information including at least one global routing table maintained by the interconnection controller and relating each of the other clusters to at least one of the global links;

providing memory mapping information maintained by the interconnection controller and relating each of the other clusters to respective portions of the remainder portion of the global memory address space;

mapping locally generated transmissions in each cluster directed to the remainder portion of the global memory address to the global links using the memory mapping information and the global routing information; and

mapping remotely generated transmissions directed to the local nodes to the local links using the local routing information.

11. An interconnection controller for use in a computer system comprising a plurality of processor clusters interconnected by a plurality of global point-to-point links and having a global memory address space associated therewith, each cluster including a plurality of local nodes and an instance of the interconnection controller interconnected by a plurality of local point-to-point links, each cluster having a local memory address space associated therewith corresponding to a first portion of the global memory address space, wherein the interconnection controller in each cluster is mapped by the associated local nodes to a remainder portion of the global memory address space exclusive of the first portion, each cluster having routing information associated with each of the local nodes for facilitating communication between the local nodes and the interconnection controller via specific ones of the local links identified in the associated routing information, the interconnection controller comprising circuitry which is operable to maintain at least one local routing table relating each of the local nodes to at least one of the local links, maintain at least one global routing table relating each of the other clusters to at least one of the global links, maintain mapping information relating each of the other clusters to respective portions of the remainder portion of the global memory address space, map locally generated transmissions directed to the remainder portion of the global memory address space the global links using the mapping information and the at least one global routing table, and map remotely generated transmissions directed to the local nodes to the local links using the at least one local routing table.

12. An integrated circuit comprising the interconnection controller of claim 11.

13. The integrated circuit of claim 12 wherein the integrated circuit comprises an application-specific integrated circuit.

14. At least one computer-readable medium having data structures stored therein representative of the interconnection controller of claim 11.

15. The at least one computer-readable medium of claim 14 wherein the data structures comprise a simulatable representation of the interconnection controller.

16. The at least one computer-readable medium of claim 15 wherein the simulatable representation comprises a netlist.

17. The at least one computer-readable medium of claim 14 wherein the data structures comprise a code description of the interconnection controller.

18. The at least one computer-readable medium of claim 17 wherein the code description corresponds to a hardware description language.