Power managed busses and arbitration

• US 7,281,148 B2
• Filed: 03/26/2004
• Issued: 10/09/2007
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Munguia, Peter R.
• Primary Examiner(s): DU, THUAN N
• Application Number:
  US10/809,970
• Publication Number:
  US 20050216607A1
• Time in Patent Office: 1,292 Days
• Field of Search: 713/501, 713/503, 713/600, 710/107, 710/305, 710/307
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A variable speed bus has its frequency adjusted based upon bandwidth requirements of active units coupled to a variable speed bus. As units coupled to the bus are stopped, bandwidth requirements are lowered and the bus frequency is reduced in response to the lowered bandwidth requirements. An arbiter selects an appropriate arbitration configuration based on which units are active and which are stopped. The arbitration configuration is adjusted to ensure that the bandwidth requirements of the active units are sustained despite the reduced clock frequency.

Claims

1. An apparatus, comprising:

a variable speed bus;

a first unit coupled to the variable speed bus;

a second unit coupled to the variable speed bus; and

an arbitration and bus clock control unit to adjust the variable speed bus frequency depending on the bandwidth requirements of the first and second units, the arbitration and bus clock control unit to monitor which of the first and second units are active and to select an appropriate arbitration configuration depending on which of the first and second units are active, wherein the arbitration and bus clock control unit is configured to adjust the arbitration configuration to ensure that the bandwidth requirements of the active units are sustained when the variable speed bus frequency is reduced.

2. The apparatus of claim 1, wherein the first unit is a host processor unit.

3. The apparatus of claim 1, wherein the second unit is a video processor unit.

4. The apparatus of claim 1, wherein the first unit is a graphics processor unit.

5. The apparatus of claim 1, wherein the second unit is a peripheral device controller unit.

6. The apparatus of claim 1, wherein the variable speed bus, the first unit, the second unit, and the arbitration and clock control unit are located on a single semiconductor die.

7. The apparatus of claim 1, wherein the arbitration and bus clock control unit is configured to adjust the arbitration configuration depending on current shared resource utilization by the active units.

8. The apparatus of claim 1, wherein the arbitration and bus clock control unit is configured to adjust the arbitration configuration depending on current shared resource utilization by the active units.

11. The system of claim 8, wherein the second device coupled to the variable speed bus is a video processor.

12. The system of claim 11, further comprising a third device coupled to the variable speed bus, the arbitration and bus clock control unit to monitor whether the third device is active and to select an appropriate arbitration configuration depending on which of the first, second, and third devices are active.

13. The system of claim 12, wherein the third device coupled to the variable speed bus is a peripheral device controller.

14. The system of claim 13, the variable speed bus being 64 bits in width.

9. A system, comprising:

a variable speed bus;

a first device coupled to the variable speed bus;

a memory coupled to the variable speed bus;

a second device coupled to the variable speed bus; and

an arbitration and bus clock control unit to adjust the variable speed bus frequency depending on the bandwidth requirements of the first and second devices, the arbitration and bus clock control unit to monitor which of the first and second devices are active and to select an appropriate arbitration configuration depending on which of the first and second devices are active, wherein the arbitration and bus clock control unit is configured to adjust the arbitration configuration to ensure that the bandwidth requirements of the active units are sustained when the variable speed bus frequency is reduced.

10. The system of claim 9, wherein the first device coupled to the variable speed bus is a processor.

15. A method, comprising:

determining which of a plurality of units coupled to a variable speed bus are active;

adjusting the clock frequency of the variable speed bus according to the bandwidth requirements of the active units; and

selecting one of a plurality of arbiter configurations depending on which of the plurality of units coupled to the variable speed bus are active, wherein selecting the one arbiter configuration comprises selecting the one of the plurality of arbiter configurations that ensures the bandwidth requirements of the active units are sustained when the clock frequency of the variable speed bus is reduced.

16. The method of claim 15, wherein determining which of a plurality of units coupled to a variable speed bus are active includes determining which of a host processor, a graphics processor, a peripheral device controller, and a video processor are active.

17. The method of claim 16, wherein adjusting the clock frequency of the variable speed bus includes setting the clock frequency to a first frequency if the host processor and the graphics controller are determined to be inactive.

18. The method of claim 17, wherein selecting one of a plurality of arbiter configurations includes selecting a first configuration if the host processor and the graphics processor are determined to be inactive.

19. The method of claim 16, wherein adjusting the clock frequency of the variable speed bus includes setting the clock frequency to a second frequency if the host processor and the graphics controller are determined to be active.

20. The method of claim 19, wherein selecting one of a plurality of arbiter configurations includes selecting a second configuration if the host processor and the graphics processor are determined to be active.