Methods and apparatus for controlling operation of a data storage system
First Claim
1. A data storage system, comprising:
- power circuitry configured to provide power signals;
storage processing circuitry configured to perform data storage operations; and
a packaged microcontroller coupled to the power circuitry and the storage processing circuitry, the packaged microcontroller having a set of input lines, a set of output lines, and control circuitry coupled to the set of input lines and the set of output lines, the control circuitry being configured to;
receive, on the set of input lines, a first set of power signals which is provided by the power circuitry to the storage processing circuitry,wait a predetermined time period in response to receipt of the first set of power signals on the set of input lines, andoutput, through the set of output lines, a set of enable signals to the power circuitry after waiting the predetermined time period, the set of enable signals directing the power circuitry to provide a second set of power signals to the storage processing circuitry;
wherein the packaged microcontroller further includes;
a set of built-in analog-to-digital converters coupled to the set of input lines and to the control circuitry, the control circuitry being configured to compare a set of binary values from the set of built-in analog-to-digital converters to a set of pre-determined thresholds to determine when all of the power signals within the set of power signals have reached levels that prevents damage to the storage processing circuitry when the second set of power signals is provided to the storage processing circuitry;
memory which stores pre-loaded code having a version identifier, the control circuitry being configured to;
compare the version identifier of the pre-loaded code with a version identifier of available new code, andreplace the pre-loaded code stored in the memory with the available new code when the version identifier of the available new code indicates that the available new code is newer than the pre-loaded code, and maintain the pre-loaded code within the memory when the version identifier of the available new code indicates that the available new code is not newer than the pre-loaded code.
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Accused Products
Abstract
A data storage system includes power circuitry configured to provide power signals, storage processing circuitry configured to perform data storage operations, and a packaged microcontroller coupled to the power circuitry and the storage processing circuitry. The packaged microcontroller has input lines, output lines, and control circuitry coupled to the input lines and the output lines. The control circuitry is configured to (i) receive, on the input lines, first power signals (e.g., voltage signals for I/O circuitry) which is provided by the power circuitry to the storage processing circuitry, (ii) wait a predetermined time period in response to receipt of the first power signals on the input lines, and (iii) output, through the output lines, enable signals to the power circuitry after waiting the predetermined time period. The enable signals directs the power circuitry to provide second power signals to the storage processing circuitry (e.g., voltage signals for core circuitry).
35 Citations
19 Claims
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1. A data storage system, comprising:
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power circuitry configured to provide power signals; storage processing circuitry configured to perform data storage operations; and a packaged microcontroller coupled to the power circuitry and the storage processing circuitry, the packaged microcontroller having a set of input lines, a set of output lines, and control circuitry coupled to the set of input lines and the set of output lines, the control circuitry being configured to; receive, on the set of input lines, a first set of power signals which is provided by the power circuitry to the storage processing circuitry, wait a predetermined time period in response to receipt of the first set of power signals on the set of input lines, and output, through the set of output lines, a set of enable signals to the power circuitry after waiting the predetermined time period, the set of enable signals directing the power circuitry to provide a second set of power signals to the storage processing circuitry; wherein the packaged microcontroller further includes; a set of built-in analog-to-digital converters coupled to the set of input lines and to the control circuitry, the control circuitry being configured to compare a set of binary values from the set of built-in analog-to-digital converters to a set of pre-determined thresholds to determine when all of the power signals within the set of power signals have reached levels that prevents damage to the storage processing circuitry when the second set of power signals is provided to the storage processing circuitry; memory which stores pre-loaded code having a version identifier, the control circuitry being configured to; compare the version identifier of the pre-loaded code with a version identifier of available new code, and replace the pre-loaded code stored in the memory with the available new code when the version identifier of the available new code indicates that the available new code is newer than the pre-loaded code, and maintain the pre-loaded code within the memory when the version identifier of the available new code indicates that the available new code is not newer than the pre-loaded code. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A packaged microcontroller for controlling a data storage system having (i) power circuitry for providing power signals and (ii) storage processing circuitry for performing data storage operations, the packaged microcontroller comprising:
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a set of input lines; a set of output lines; control circuitry coupled to the set of input lines and the set of output lines, the control circuitry being configured to; receive, on the set of input lines, a first set of power signals which is provided by the power circuitry to the storage processing circuitry, wait a predetermined time period in response to receipt of the first set of power signals on the set of input lines; and output, through the set of output lines, a set of enable signals to the power circuitry after waiting the predetermined time period, the set of enable signals directing the power circuitry to provide a second set of power signals to the storage processing circuitry; a set of built-in analog-to-digital converters coupled to the set of input lines and to the control circuitry, the control circuitry being configured to compare a set of binary values from the set of built-in analog-to-digital converters to a set of pre-determined thresholds to determine when all of the power signals within the set of power signals have reached levels that prevents damage to the storage processing circuitry when the second set of power signals is provided to the storage processing circuitry; and memory which stores pre-loaded code having a version identifier, the control circuitry being configured to; compare the version identifier of the pre-loaded code with a version identifier of available new code; and replace the pre-loaded code stored in the memory with the available new code when the version identifier of the available new code indicates that the available new code is newer than the pre-loaded code, and maintain the pre-loaded code within the memory when the version identifier of the available new code indicates that the available new code is not newer than the pre-loaded code. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A packaged microcontroller for controlling a data storage system having (i) power circuitry for providing power signals and (ii) storage processing circuitry for performing data storage operations, the packaged microcontroller comprising:
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a set of input lines; a set of output lines; control circuitry coupled to the set of input lines and the set of output lines, the control circuitry being configured to; receive, on the set of input lines, a first set of power signals which is provided by the power circuitry to the storage processing circuitry, wait a predetermined time period in response to receipt of the first set of power signals on the set of input lines; and output, through the set of output lines, a set of enable signals to the power circuitry after waiting the predetermined time period, the set of enable signals directing the power circuitry to provide a second set of power signals to the storage processing circuitry; a set of built-in analog-to-digital converters coupled to the set of input lines and to the control circuitry, the control circuitry being configured to compare a set of binary values from the set of built-in analog-to-digital converters to a set of pre-determined thresholds to determine when all of the power signals within the set of power signals have reached levels that prevents damage to the storage processing circuitry when the second set of power signals is provided to the storage processing circuitry; a dedicated memory location; and memory having a main portion which stores pre-loaded main code and a secondary portion which stores pre-loaded secondary code, wherein the control circuitry is further configured to; access the dedicated memory location to determine whether a flag is set to indicated that a code replacement routine is in progress, and run (i) the pre-loaded main code stored in the main portion of the memory when the dedicated memory location is not set with the flag, and (ii) the secondary code stored in the secondary portion of the memory when the dedicated memory location is set with the flag.
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14. In a packaged microcontroller, a method for controlling a data storage system having (i) power circuitry for providing power signals and (ii) storage processing circuitry for performing data storage operations, the method comprising:
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receiving, on a set of input lines of the packaged microcontroller, a first set of power signals which is provided by the power circuitry to the storage processing circuitry; waiting a predetermined time period in response to receipt of the first set of power signals on the set of input lines; and outputting, on a set of output lines of the packaged microcontroller, a set of enable signals to the power circuitry after waiting the predetermined time period, the set of enable signals directing the power circuitry to provide a second set of power signals to the storage processing circuitry; wherein the packaged microcontroller includes; a set of built-in analog-to-digital converters coupled to the set of input lines, and wherein receiving the first set of power signals includes; comparing a set of binary values from the set of built-in analog-to-digital converters to a set of pre-determined thresholds to determine when all of the power signals within the set of power signals have reached levels that prevents damage to the storage processing circuitry when the second set of power signals is provided to the storage processing circuitry; and memory which stores pre-loaded code having a version identifier, and wherein the method further comprises; comparing the version identifier of the pre-loaded code with a version identifier of available new code; and replacing the pre-loaded code stored in the memory with the available new code when the version identifier of the available new code indicates that the available new code is newer than the pre-loaded code, and maintaining the pre-loaded code within the memory when the version identifier of the available new code indicates that the available new code is not newer than the pre-loaded code. - View Dependent Claims (15, 16, 17, 18)
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19. In a packaged microcontroller, a method for controlling a data storage system having (i) power circuitry for providing power signals and (ii) storage processing circuitry for performing data storage operations, the method comprising:
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receiving, on a set of input lines of the packaged microcontroller, a first set of power signals which is provided by the power circuitry to the storage processing circuitry; waiting a predetermined time period in response to receipt of the first set of power signals on the set of input lines; and outputting on a set of output lines of the packaged microcontroller, a set of enable signals to the power circuitry after waiting the predetermined time period, the set of enable signals directing the power circuitry to provide a second set of power signals to the storage processing circuitry; wherein the packaged microcontroller includes; a set of built-in analog-to-digital converters coupled to the set of input lines, and wherein receiving the first set of power signals includes; comparing a set of binary values from the set of built-in analog-to-digital converters to a set of pre-determined thresholds to determine when all of the power signals within the set of power signals have reached levels that prevents damage to the storage processing circuitry when the second set of power signals is provided to the storage processing circuitry; and memory having a main portion which stores pre-loaded main code and a secondary portion which stores pre-loaded secondary code, and wherein the method further comprises; accessing a dedicated memory location to determine whether a flag is set to indicated that a code replacement routine is in progress; and running (i) the pre-loaded main code stored in the main portion of the memory when the dedicated memory location is not set with the flag, and (ii) the secondary code stored in the secondary portion of the memory when the dedicated memory location is set with the flag.
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Specification