Systems, methods and computer programs for calibrating an automated circuit test system

• US 7,281,181 B2
• Filed: 06/27/2005
• Issued: 10/09/2007
• Est. Priority Date: 06/27/2005
• Status: Expired due to Fees

• Current Assignee: Verigy Limited (Advantest Corporation)
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Sugihara, Noriyuki
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US11/168,033
• Publication Number:
  US 20070022347A1
• Time in Patent Office: 834 Days
• Field of Search: None
• US Class Current: 714/724
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence

Abstract

In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A second calibration unit is then electrically coupled between the plurality of drivers and comparators, and an AC timing calibration procedure is executed to determine a timing delay for each of a second set of relationships. The first and second calibration units comprise fixed wiring paths that respectively couple pairs of the drivers and comparators in accord with the first and second sets of relationships. A set of equations is solved based on the timing delays and driver/comparator relationships to determine relative timing errors introduced by signal paths of the test system including the drivers and comparators.

Claims

1. A method for calibrating an automated circuit test system, comprising:

electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, the first calibration unit comprising fixed wiring paths that couple the drivers and comparators to form a first set of signal paths between a first set of driver and comparator pairs;

executing a resistance check while the first calibration unit is coupled between the plurality of drivers and comparators, thereby determining resistances for the first set of signal paths;

electrically coupling a second calibration unit between the plurality of drivers and comparators, the second calibration unit comprising fixed wiring paths that couple the drivers and comparators to form a second set of signal paths between a second set of driver and comparator pairs;

executing a resistance check while the second calibration unit is coupled between the plurality of drivers and comparators, thereby determining resistances for the second set of signal paths; and

solving a set of equations based on the resistances and the first and second sets of driver and comparator pairs to determine i) relative resistances imparted by signal paths of the test system that include the drivers, and ii) relative resistances imparted by signal paths of the test system that include the comparators.

2. The method of claim 1, wherein the set of equations is solved, in part, by i) setting a resistance associated with a reference one of the signal paths including one of the drivers to a default value, and ii) setting a resistance associated with a reference one of the signal paths including one of the comparators to a default value.