Method and apparatus for automatically checking circuit layout routing

• US 7,281,232 B1
• Filed: 06/23/2004
• Issued: 10/09/2007
• Est. Priority Date: 02/12/2004
• Status: Expired due to Fees

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Chayut, Ira G., Nicolino, Sam J. Jr.
• Primary Examiner(s): Whitmore; Stacy A.
• Assistant Examiner(s): Dimyan; Magid Y.
• Application Number:
  US10/875,997
• Time in Patent Office: 1,203 Days
• Field of Search: 716 12- 15
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method and apparatus for checking topology layout routing is described. A method for checking topology layout routing includes accessing actual topology layout information of a circuit. Then, compliance topology information is established. Then, the method checks the actual topology layout information complies with the compliance topology information. Then, the method presents violations of the compliance topology information.

Claims

1. A method for checking circuit routing, comprising:

a) accessing actual topology layout information of a circuit, wherein said actual topology layout information is in a vector format that is derived from a topology of said circuit;

b) establishing compliance topology information, wherein said compliance topology information is based on custom design information that describes basic information of said circuit;

c) checking said actual topology layout information complies with said compliance topology information; and

d) presenting violations of said compliance topology information.

2. The method of claim 1, wherein said circuit is formed in a printed circuit board (PCB) circuit.

3. The method of claim 1, wherein said circuit is formed in a substrate.

4. The method of claim 1, wherein said actual topology layout information comprises:

a pins file describing locations of pins in said circuit;

a geometry file describing wire segments in said circuit; and

a via file describing locations of vias in said circuit.

5. The method of claim 1, wherein b) comprises:

b1) accessing custom design information of said circuit; and

b2) selecting said compliance topology information applicable to various topology layouts.

6. The method of claim 5, wherein said custom design information comprises identifying information of a chipset in said circuit.

7. The method of claim 5, wherein said custom design information comprises identifying information of a media processor in said circuit.

8. The method of claim 5, wherein said compliance topology information comprises:

design rules that provide geometric constraints for said topology based on said custom design information.

9. The method of claim 8, wherein said design rules are taken from a list comprising:

trace width;

minimum length; and

maximum length.

10. The method of claim 8, wherein said design rules are taken from a list comprising:

serpentine space;

group spacing;

group to group spacing; and

interface to interface spacing.

11. The method of claim 8, wherein said design rules are taken from a list comprising:

termination type;

termination maximum stub length; and

termination rail.

12. The method of claim 5, wherein said compliance topology information comprises:

design knowledge that maps a plurality of signals in said circuit based on said custom design information.

13. The method of claim 1, wherein said c) further comprises˜

checking trace lengths and widths in said actual topology layout information.

14. The method of claim 1, wherein said c) further comprises:

checking spacing in said actual topology layout information.

15. The method of claim 1, wherein said c) further comprises:

checking power plane boundaries of signals in said actual topology layout information.

16. The method of claim 1, wherein said c) further comprises:

checking termination of nets in said actual topology layout information.

17. A system for checking topology layout routing, comprising:

a compliance topology builder for building compliance topology information based on custom design information;

a translator for translating between actual topology layout information and said compliance topology information;

a compliance checker for checking said actual topology layout information complies with said compliance topology information.

18. The system of claim 17, further comprising:

a calculator for calculating parameters of said actual topology layout information.

19. The system of claim 17, wherein said compliance checker checks that routing of traces derived from said actual topology layout information complies with said compliance topology information.

20. The system of claim 17, wherein said compliance topology builder comprises:

a rules file parser for automatically accessing associated design rules that provide geometric constraints for said actual topology layout information.

21. The system of claim 17, wherein said compliance topology builder comprises:

a knowledge file parser for automatically accessing associated design knowledge that maps a plurality of signals in said actual topology layout information.

22. The system of claim 17, wherein said compliance checker performs checks comprising:

trace lengths checks;

spacing checks;

trace width checks;

trace termination checks; and

power plane checks.

23. A computer system comprising:

a processor for processing information; and

a computer readable memory coupled to said processor and containing program instructions that, when executed cause said processor to implement a method for checking circuit routing, comprising;

a) accessing actual topology layout information of a circuit wherein said actual topology layout information is in a vector format that is derived from a topology of said circuit;

b) establishing compliance topology information wherein said compliance topology information is based on custom design information that describes basic information of said circuit;

c) checking said actual topology layout information complies with said compliance topology information; and

d) presenting violations of said compliance topology information.

24. The computer system of claim 23, wherein said circuit is formed in a printed circuit board (PCB).

25. The computer system of claim 23, wherein said circuit is formed in a substrate.

26. The computer system of claim 23, wherein said actual topology layout information comprises:

a pins file describing locations of pins in said circuit;

a geometry file describing wire segments in said circuit; and

a via file describing locations of vias in said circuit.

27. The computer system of claim 23, wherein b) in said method comprises:

b1) accessing custom design information of said circuit; and

b2) selecting said compliance topology information applicable to various topology layouts.

28. The computer system of claim 27, wherein said custom design information comprises identifying information of a chipset in said circuit.

29. The computer system of claim 27, wherein said custom design information comprises identifying information of a media processor in said circuit.

30. The computer system of claim 27, wherein said compliance topology information comprises:

design rules that provide geometric constraints for said circuit based on said custom design information.

31. The computer system of claim 30, wherein said design rules are taken from a list comprising:

trace width;

minimum length; and

maximum length.

32. The computer system of claim 30, wherein said design rules are taken from a list comprising:

serpentine space;

group spacing;

group to group spacing; and

interface to interface spacing.

33. The computer system of claim 30, wherein said design rules are taken from a list comprising:

termination type;

termination maximum stub length; and

termination rail.

34. The computer system of claim 27, wherein said compliance topology information comprises:

design knowledge that maps a plurality of signals in said topology based on said custom design information.

35. The computer system of claim 23, wherein said c) in said method further comprises:

checking trace lengths and widths in said actual topology layout information.

36. The computer system of claim 23, wherein said c) in said method further comprises:

checking spacing in said actual topology layout information.

37. The computer system of claim 23, wherein said c) in said method further comprises:

checking power plane boundaries of signals in said actual topology layout information.

38. The computer system of claim 23, wherein said c) in said method further comprises:

checking termination of nets in said actual topology layout information.

39. A computer readable medium for storing program instructions that, when executed implements a method for checking circuit routing, comprising:

a) accessing actual topology layout information of a circuit wherein said actual topology layout information is in a vector format that is derived from a topology of said circuit;

b) establishing compliance topology information wherein said compliance topology information is based on custom design information that describes basic information of said circuit;

c) checking said actual topology layout information complies with said compliance topology information; and

d) presenting violations of said compliance topology information.

40. The method of claim 39, wherein said circuit is formed in a printed circuit board (PCB) circuit.

41. The method of claim 39, wherein said compliance topology information comprises:

design rules that provide geometric constraints for said topology based on said custom design information.

42. The method of claim 39, wherein said compliance topology information comprises:

design knowledge that maps a plurality of signals in said circuit based on said custom design information.