Method and apparatus for implementing a circuit design for integrated circuitry on a circuit board

• US 7,281,233 B1
• Filed: 05/27/2005
• Issued: 10/09/2007
• Est. Priority Date: 05/27/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Sivasubramaniam, Suresh
• Primary Examiner(s): WHITMORE, STACY
• Application Number:
  US11/140,020
• Time in Patent Office: 865 Days
• Field of Search: 716/4, 716/7, 716/16, 716/18, 716/10, 716 13- 15, 71/15
• US Class Current: 716/105
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Method and apparatus for implementing a circuit design for at least one integrated circuit on a circuit board is described. In one example, a logical description of the circuit design is obtained. For example, a functional description of the circuit design may be synthesized to produce the logical description. Logical pins in the logical description are assigned to input/output (I/O) elements of the at least one integrated circuit, and the logical description is placed and routed for the at least one integrated circuit, based on external constraint data associated with the circuit board and internal logic constraint data associated with each of the at least one integrated circuit.

Claims

1. A method of implementing a circuit design for at least one integrated circuit on a circuit board, comprising:

obtaining a logical description of the circuit design;

assigning logical pins in the logical description to input/output (I/O) elements of the at least one integrated circuit, and placing and routing the logical description for the at least one integrated circuit, based on a cost function that is dependent upon external constraint data associated with the circuit board and internal logic constraint data associated with each of the at least one integrated circuit; and

generating a physical design for the at least one integrated circuit.

2. The method of claim 1, further comprising:

determining whether the internal logic constraint data and the external constraint data is satisfied;

if either the internal logic constraint data or the external constraint data is not satisfied, obtaining constraint failure data and repeating the step of assigning to compensate for the constraint failure data.

3. The method of claim 1, wherein the step of assigning the logical pins in the logical description comprises:

assigning the logical pins to the I/O elements of the at least one integrated circuit based on the external constraint data to produce pin constraint data; and

placing and routing the logical description for the at least one integrated circuit based on the pin constraint data and the internal logic constraint data.

4. The method of claim 3, further comprising:

determining whether the internal logic constraint data is satisfied;

if the internal logic constraint data is not satisfied, obtaining constraint failure data and re-assigning the logical pins in the logical description to the I/O elements based on the external constraint data and the constraint failure data to modify the pin constraint data; and

repeating the steps of placing and routing, determining, and obtaining the constraint failure data until the internal logic constraint data is satisfied.

5. The method of claim 1, wherein the step of assigning the logical pins in the logical description comprises:

placing and routing the logical description for the at least one integrated circuit based on the internal logic constraint data to produce place and route constraint data; and

assigning the logical pins to the I/O elements of the at least one integrated circuit based on the external constraint data and the place and route constraint data.

6. The method of claim 5, further comprising:

determining whether the external constraint data is satisfied;

if the external constraint data is not satisfied, obtaining constraint failure data and re-placing and re-routing the logical description based on the internal logic constraint data and the constraint failure data to modify the place and route constraint data; and

repeating the steps of assigning the logical pins to the I/O elements, determining, and obtaining the constraint failure data until the external constraint data is satisfied.

7. The method of claim 1, further comprising:

automatically generating schematic data for the circuit design; and

automatically performing placement and layout of the at least one integrated circuit on the circuit board based on the schematic data.

8. The method of claim 1, wherein the at least one integrated circuit comprises a plurality of integrated circuits and wherein the step of assigning further comprises:

partitioning the logical description among the plurality of integrated circuits.

9. The method of claim 1, wherein the step of obtaining the logical description comprises:

obtaining a functional description of the circuit design;

synthesizing the functional description to produce the logical description.

10. The method of claim 9, wherein the at least one integrated circuit comprises a plurality of integrated circuits, and wherein the step of synthesizing comprises:

partitioning the logical description among the plurality of integrated circuits.

11. The method of claim 1, wherein the external constraint data comprises constraints based on at least one of trace lengths on the circuit board, trace widths on the circuit board, a number of layers of the circuit board, or a number of wire crossings permitted on the circuit board.

12. A system for implementing a circuit design for at least one integrated circuit on a circuit board, comprising:

a synthesis tool for synthesizing a functional description of the circuit design to produce a logical description; and

a place and route tool for assigning logical pins in the logical description to input/output (I/O) elements of the at least one integrated circuit, and placing and routing the logical description for the at least one integrated circuit, based on a cost function that is dependent upon external constraint data associated with the circuit board and internal logic constraint data associated with each of the at least one integrated circuit;

wherein the system generates a physical design for the at least one integrated circuit.

13. The system of claim 12, wherein the place and route tool is further configured to determining whether the internal logic constraint data and the external constraint data is satisfied, and if either the internal logic constraint data or the external constraint data is not satisfied at step, obtain constraint failure data and repeat pin assignment and place and route to compensate for the constraint failure data.

14. The system of claim 12, wherein the place and route tool is configured to assign the logical pins to the I/O elements of the at least one integrated circuit based on the external constraint data to produce pin constraint data, and place and route the logical description for the at least one integrated circuit based on the pin constraint data and the internal logic constraint data.

15. The system of claim 12, wherein the place and route tool is configured to place and route the logical description for the at least one integrated circuit based on the internal logic constraint data to produce place and route constraint data, and assign the logical pins to the I/O elements of the at least one integrated circuit based on the external constraint data and the place and route constraint data.

16. The system of claim 12, further comprising:

a schematic tool for automatically generating schematic data for the circuit design; and

a placement and layout tool for automatically performing placement and layout of the at least one integrated circuit on the circuit board based on the schematic data.

17. The system of claim 15, wherein the at least one integrated circuit comprises a plurality of integrated circuits, and wherein the synthesis tool is configured to partition the functional description among the plurality of integrated circuits.

18. The system of claim 15, wherein the at least one integrated circuit comprises a plurality of integrated circuits, and wherein the place and route tool is configured to partition the functional description among the plurality of integrated circuits.

19. The system of claim 15, wherein the external constraint data comprises constraints based on at least one of trace lengths on the circuit board, trace widths on the circuit board, a number of layers of the circuit board, or a number of wire crossings permitted on the circuit board.

20. Apparatus for implementing a circuit design for at least one integrated circuit on a circuit board, comprising:

means for obtaining a logical description of the circuit design;

means for assigning logical pins in the logical description to input/output (I/O) elements of the at least one integrated circuit, and placing and routing the logical description for the at least one integrated circuit, based on a cost function that is dependent upon external constraint data associated with the circuit board and internal logic constraint data associated with each of the at least one integrated circuit; and

means for generating a physical design for the at least one integrated circuit.