Integrated resistance cancellation in temperature measurement systems

• US 7,281,846 B2
• Filed: 08/23/2004
• Issued: 10/16/2007
• Est. Priority Date: 08/23/2004
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: McLeod, Scott C.
• Primary Examiner(s): VERBITSKY, GAIL KAPLAN
• Application Number:
  US10/924,176
• Publication Number:
  US 20060039445A1
• Time in Patent Office: 1,149 Days
• Field of Search: 374/163, 374/183, 374/178, 327/512, 327/513, 327/109, 327/336
• US Class Current: 374/178
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence

Abstract

A temperature measurement device may be implemented by coupling a PN-junction, which may be comprised in a diode, to an analog-to-digital converter (ADC) that comprises an integrator. Different currents may be successively applied to the diode, resulting in different V_BE values across the diode. The ΔV_BE values thus obtained may be successively integrated. Appropriate values for the different currents may be determined based on a set of mathematical equations, each equation relating the V_BE value to the temperature of the diode, the current applied to the diode and parasitic series resistance associated with the diode. When the current sources with the appropriate values are sequentially applied to the diode and the resulting diode voltage differences are integrated by the integrator comprised in the ADC, the error in the temperature measurement caused by series resistance is canceled in the ADC, and an accurate temperature reading of the diode is obtained from the output of the ADC.

Claims

1. A temperature monitoring system comprising:

an analog-to-digital converter (ADC);

a semiconductor device coupled to the ADC, wherein the semiconductor device has a substantially defined generally non-linear input-output characteristic that varies with temperature and is subject to effects of parasitic resistance; and

a plurality of input devices operable to provide a sequence of input signals to the semiconductor device, wherein each input signal of the sequence of input signals is generated by one of the plurality of input devices;

wherein the semiconductor device is operable to generate a sequence of output signals and provide the sequence of output signals to the ADC, wherein each output signal of the sequence of output signals is generated in response to a respective input signal of the sequence of input signals; and

wherein the ADC is operable to produce a numeric value from the sequence of output signals, the numeric value corresponding to a temperature of the semiconductor device;

wherein the plurality of input devices is operable to substantially eliminate an error component from the numeric value by providing a specific sequence of input signals to the semiconductor device, wherein the error component is caused by the effects of parasitic resistance.

2. The system of claim 1, wherein the semiconductor device comprises a PN-junction.

3. The system of claim 2, wherein the output signal is a base-emitter voltage developed across the PN-junction.

4. The system of claim 2, wherein the PN-junction is comprised in a diode.

5. The system of claim 2, wherein the PN-junction is comprised in a bipolar junction transistor (BJT).

6. The system of claim 1, wherein the plurality of input devices is a plurality of current sources, and the input signals are input currents.

7. The system of claim 1, wherein the plurality of input devices comprises three or more current sources and the input signals comprise input currents.

8. The system of claim 1, wherein the ADC is one of:

a pipeline ADC;

a cyclic ADC;

a delta-sigma ADC;

a successive approximation ADC; and

an integrating ADC.

9. The system of claim 1, wherein the ADC comprises an integrating sample-and-hold circuit.

10. A method for monitoring temperature, the method comprising:

determining a specific sequence of input signals from a plurality of available input signals, wherein each one of the specific sequence of input signals has a respective value, resulting in a sequence of values corresponding to the sequence of input signals, wherein a combination of the sequence of values adds up to zero;

applying the specific sequence of input signals to a device, the device having a substantially defined generally non-linear input-output characteristic that varies with temperature and is subject to effects of parasitic resistance, the device producing a sequence of output signals in response to the specific sequence of input signals, wherein each output signal of the sequence of output signals corresponds to a respective input signal of the specific sequence of input signals;

developing a compounded signal by combining each subsequent output signal of the sequence of output signals; and

generating a numeric value corresponding to the compounded signal, the numeric value further corresponding to a temperature of the device;

wherein in performing said determining the specific sequence of input signals, an error component is substantially eliminated from the numeric value during said developing the compounded signal, wherein the error component is caused by the effects of parasitic resistance.

11. The method of claim 10, wherein the device comprises a PN-junction.

12. The method of claim 11, wherein the device is one of:

a diode; and

a BJT.

13. The method of claim 12, wherein each input signal of the specific sequence of input signals is an input current, and each output signal of the sequence of output signals is a base-emitter voltage of the PN-junction.

14. The method of claim 13, wherein said combining each subsequent output signal comprises integrating each subsequent output signal.

15. The method of claim 14, wherein said integrating is performed by an integrating sample and hold circuit.

16. The method of claim 15, wherein the integrating sample-and-hold circuit is comprised in an ADC.

17. The method of claim 16, wherein the ADC is one of:

a delta-sigma ADC;

a cyclic ADC;

a pipeline ADC;

a successive approximation ADC; and

an integrating ADC.

18. The method of claim 16, wherein said generating and outputting the numeric value is performed by the ADC.

19. The method of claim 13, wherein each input current is generated by one of a specified number of current sources.

20. A method for monitoring temperature, the method comprising:

generating a plurality of input currents, each one of the plurality of input currents having a different value;

applying selected ones of the plurality of input currents in a specified sequence to a PN-junction, wherein a combination of the selected ones of the plurality of input currents adds up to zero, said applying resulting in a sequence of base-emitter voltages of the PN-junction, wherein each base-emitter voltage of the sequence of base-emitter voltages corresponds to a respective selected one of the plurality of input currents being applied to the PN-junction, and wherein one or more of the selected ones of the plurality of input currents are operable to be applied to the PN-junction more than once in the specified sequence;

developing a voltage difference signal by integrating each base-emitter voltage of the sequence of base-emitter voltages; and

generating a numeric value from the voltage difference signal, the numeric value corresponding to a temperature of the PN-junction, wherein in performing said applying selected ones of the plurality of input currents in the specified sequence, an error component is substantially eliminated from the numeric value during said developing the voltage difference signal, wherein the error component is caused by effects of parasitic resistance in series with the PN-junction.

21. The method of claim 20, wherein each input current of the plurality of input currents is generated by a respective current source.

22. The method of claim 20, wherein the plurality of input currents comprises at least three input currents.

23. The method of claim 20, wherein a value relationship between the selected ones of the plurality of input currents is determined based on a set of mathematical equations, each equation of the set of mathematical equations relating a respective base-emitter voltage of the sequence of base-emitter voltages to:

the respective selected one of the plurality of input currents applied to the PN-junction resulting in the respective base-emitter voltage;

a temperature of the PN-junction corresponding to the respective selected one of the plurality of input currents applied to the PN-junction; and

a value of the parasitic resistance in series with the PN-junction.

24. A temperature monitoring system comprising:

an analog-to-digital converter (ADC);

an integrating sample-and-hold circuit coupled to the ADC;

a semiconductor device coupled to the integrating sample-and-hold circuit, wherein the semiconductor device has a substantially defined generally non-linear input-output characteristic that varies with temperature and is subject to effects of parasitic resistance; and

a plurality of input devices operable to provide a sequence of input signals to the semiconductor device, wherein each one of the sequence of input signals has a respective value, resulting in a sequence of values corresponding to the sequence of input signals, wherein each one of the plurality of input signals is generated by a corresponding one of the plurality of input devices, and wherein a combination of the sequence of values adds up to zero;

wherein the semiconductor device is operable to generate a sequence of output signals and provide the sequence of output signals to the integrating sample-and-hold circuit, wherein each output signal of the sequence of output signals is generated in response to a respective input signal of the specified sequence of input signals;

wherein the integrating sample-and-hold circuit is operable to produce a compounded output signal from the sequence of output signals, wherein the compounded output signal corresponds to a temperature of the semiconductor device, wherein the plurality of input devices is operable to substantially eliminate an error component from the compounded output signal by providing a specific sequence of input signals to the semiconductor device, wherein the error component is caused by the effects of parasitic resistance; and

wherein the ADC is operable to produce a numeric value based on the compounded output signal, the numeric value corresponding to the temperature of the semiconductor device.

25. The system of claim 24, wherein the semiconductor device comprises a PN-junction.

26. The system of claim 25, wherein the output signal is a base-emitter voltage developed across the PN-junction.

27. The system of claim 25, wherein the PN-junction is comprised in a diode.

28. The system of claim 25, wherein the PN-junction is comprised in a bipolar junction transistor (BJT).

29. The system of claim 24, wherein the plurality of input devices is a plurality of current sources, and the input signals are input currents.

30. The system of claim 24, wherein the plurality of input devices comprises three or more current sources and the input signals comprise input currents.

31. The system of claim 24, wherein the ADC is one of:

a pipeline ADC;

a cyclic ADC;

a delta-sigma ADC;

a successive approximation ADC; and

an integrating ADC.