Printed circuit board including embedded chips and method of fabricating the same using plating

• US 7,282,394 B2
• Filed: 07/11/2005
• Issued: 10/16/2007
• Est. Priority Date: 12/30/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Cho, Suk Hyeon, Ryu, Chang Sup, Lee, Doo Hwan
• Primary Examiner(s): Brewster; William M.
• Application Number:
  US11/179,864
• Publication Number:
  US 20060145331A1
• Time in Patent Office: 827 Days
• Field of Search: 438/118, 438/124, 438/125, 257/E23.131
• US Class Current: 438/118
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/10636 : Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4623 : the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A method of fabricating a printed circuit board (PCB) including embedded chips, composed of forming a hollow portion for chip insertion through a substrate, inserting the chip into the hollow portion, fixing the chip to the substrate by use of a plating process to form a central layer having an embedded chip, and then laminating a non-cured resin layer and a circuit layer having a circuit pattern on the central layer. Also, a PCB including embedded chips fabricated using the above method is provided.

Claims

1. A method of fabricating a printed circuit board including embedded chips, comprising the steps of:

forming a hollow portion to dispose a chip and a via hole through a substrate;

inserting the chip into the hollow portion;

plating the surface of the substrate after the chip has been inserted into the hollow portion, such that the plating is formed in spaces defined between the chip and the hollow portion;

forming circuit patterns on both an upper and a lower surface of the substrate to form a central layer; and

laminating one or more circuit layers and one or more insulating layers on the substrate.

2. The method as set forth in claim 1, wherein the step of inserting the chip into the hollow portion further comprises the step of attaching an adhesive sheet to one surface of the substrate before insertion of the chip into the hollow portion.

3. The method as set forth in claim 2, wherein the step of plating the entire surface of the substrate further comprises the step of removing the adhesive sheet.

4. The method as set forth in claim 3, wherein the step of plating the entire surface of the substrate further comprises the step of performing a plating process after the removal of the adhesive sheet.

5. The method as set forth in claim 1, wherein the step of forming the circuit patterns on both the upper and the lower surface of the substrate further comprises the step of etching both the upper and the lower surface of the substrate to form the circuit patterns thereon.

6. The method as set forth in claim 1, wherein the laminating step further comprises the steps of:

alternately laminating one or more non-cured resin layers and the one or more circuit layers on the central layer;

laminating copper foil layers on both outermost layers of the substrate;

heating and compressing the laminated non-cured resin layers, the circuit layers, and the copper foil layers; and

forming the circuit patterns on the copper foil layers of the substrate.