Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction

• US 7,282,400 B2
• Filed: 02/21/2006
• Issued: 10/16/2007
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Reinberg, Alan R.
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/358,583
• Publication Number:
  US 20060141697A1
• Time in Patent Office: 602 Days
• Field of Search: 438/193, 438/242, 438/270, 438/304
• US Class Current: 438/193
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: Y10S 438/973 Substrate orientation

Abstract

Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure'"'"'s channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Claims

1. A method of forming a transistor, comprising:

forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;

forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween; and

wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.

2. The method of claim 1, wherein the electrical current across the channel region is in a <

110>

direction.

3. The method of claim 1, wherein forming the trench in a silicon wafer includes forming a trench in a silicon wafer with a top surface in the (100) crystal plane orientation.

4. A method of forming a transistor, comprising:

forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;

forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes;

forming a doped material structure against the wall of the trench;

diffusing dopants from the doped material structure into the wall of the trench;

removing the doped material structure from the trench; and

wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.

5. The method of claim 4, wherein forming the trench in a silicon wafer includes forming a trench in a silicon-on-insulator (SOI) silicon wafer.

6. The method of claim 4, wherein the electrical current across the channel region is in a <

110>

direction.

7. The method of claim 4, wherein forming a doped material structure includes forming a doped glass structure.

8. The method of claim 4, wherein diffusing dopants from the doped material structure includes rapid thermal annealing.

9. The method of claim 4, further including forming an Si3N4 diffusion barrier layer in a bottom of the trench prior to forming the doped material structure within the trench.

10. A method of forming a transistor, comprising:

forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;

forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes;

ion implanting dopants into the wafer surface prior to forming the trench to form doped regions of a first type within a surface wafer material of a second type;

forming the trench between ion implanted regions after formation of the doped regions; and

wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.

11. The method of claim 10, wherein the doped regions include n-type dopants and the channel includes p-type dopants.

12. The method of claim 10, wherein the doped regions include p-type dopants and the channel includes n-type dopants.

13. The method of claim 10, wherein forming the trench in a silicon wafer includes forming a trench in a silicon wafer with a top surface in the (100) crystal plane orientation.

14. The method of claim 10, wherein the electrical current across the channel region is in a <

110>

direction.

15. A method of forming a transistor, comprising:

forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;

forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes angled ion implanting dopants into the trench wall to form doped regions of a first type within a wall material of a second type; and

wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.

16. The method of claim 15, wherein the doped regions include n-type dopants and the channel includes p-type dopants.

17. The method of claim 15, wherein the doped regions include p-type dopants and the channel includes n-type dopants.

18. The method of claim 15, wherein forming the trench in a silicon wafer includes forming a trench in a silicon wafer with a top surface in the (111) crystal plane orientation.

19. The method of claim 15, wherein the electrical current across the channel region is in a <

110>

direction.

20. A method of forming a memory device, comprising:

forming a number of memory cells, each cell including at least one transistor, wherein forming the transistor includes;

forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;

forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween;

wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer; and

forming storage and access circuitry coupled to the number of memory cells.

21. The method of claim 20, wherein forming a number of memory cells includes forming a number of dynamic random access memory (DRAM) cells.

22. The method of claim 20, wherein forming the transistor includes forming a p-channel transistor.

23. A method of forming an electronic system, comprising:

forming a memory device coupled to a processor, wherein forming the memory device includes forming a number of memory cells, each cell including at least one transistor, wherein forming the transistor includes;

forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;

forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween;

wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer; and

forming storage and access circuitry coupled to the number of memory cells.

24. The method of claim 23, wherein forming a memory device includes forming a dynamic random access memory (DRAM).

25. The method of claim 23, wherein the electrical current across the channel region is in a <

110>

direction.

26. The method of claim 23, wherein forming the trench in a silicon wafer includes forming a trench in a silicon wafer with a top surface in the (100) crystal plane orientation.