System and method for IDDQ measurement in system on a chip (SOC) design

• US 7,282,905 B2
• Filed: 12/10/2004
• Issued: 10/16/2007
• Est. Priority Date: 12/10/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Scott, David B., Mair, Hugh T., Chen, Wei, Ko, Uming
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US11/010,135
• Publication Number:
  US 20060125470A1
• Time in Patent Office: 1,040 Days
• Field of Search: None
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3012 Built-In-Current test [BIC]

Abstract

System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.

Claims

1. A switch structure comprising:

a plurality of power sub-domains;

a pluraiity of main switches, wherein each main switch selectively couples a different power sub-domain to a power supply;

a plurality of IDDQ switches, wherein each IDDQ switch selectively couples a power sub-domain to a VIDDQ pin, wherein there is one main switch and one IDDQ switch for each power sub-domain; and

a plurality of pi-switches coupled between power sub-domains.

2. The switch structure of claim 1, wherein all main switches are coupled to a a single power supply and wherein all IDDQ switches are coupled to a single VIDDQ pin.

3. The switch structure of claim 1 further comprising a current measuring device coupled to the VIDDQ pin and operable to measure a current drawn.

4. The switch structure of claim 3 further comprising a scan memory operable to store test vectors from a measurement of the current drawn.

7. The switch structure of claim 1, wherein the main switches and pi-switches comprise MOSFET transistors and a width of the pi-switches MOSFET transistors is smaller than a width of the main switches MOSFET transistors.

5. The switch structure of daim 1 further comprising a current measurinq device coupled to the VIDDQ pin and operable to measure a current drawn and wherein the main switches and pi-switches comprise MOSFET transistors.

6. The switch structure of claim 5 further comprising a scan memory operable to store test vectors from a measurement of the current drawn.

8. A switch structure comprising:

a plurality of main switches, wherein each main switch selectively couples a power sub-domain to a power supply;

a plurality of IDDQ switches, wherein each IDDQ switch selectively couples a power sub-domain to a VIDDQ pin, wherein there is one main switch and ore IDDQ switch for each power sub-domain;

a plurality of pi-switches coupled between power sub-domains;

a current measuring device coupled to the VIDDQ pin and operable to measure a current drawn and wherein the main switches and pi-switches comprise MOSFET transistors;

wherein a width of the pi-switches MOSFET transistors is smaller than a width of the main switches MOSFET transistors; and

a scan memory operable to store test vectors from a measurement of the current drawn.