Semiconductor device with electrode pads for test probe

• US 7,282,940 B2
• Filed: 03/31/2005
• Issued: 10/16/2007
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Hirai, Miho
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US11/094,673
• Publication Number:
  US 20050218916A1
• Time in Patent Office: 929 Days
• Field of Search: None
• US Class Current: 324/754.03
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05096 Uniform arrangement, i.e. array
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor device includes a plurality of I/O regions provided in a peripheral region of the semiconductor device. Each of the plurality of I/O regions includes an electrode pad. The electrode pad has a test probe area and a bonding area which are separately provided, and a test probe is made to contact the test probe area and an external electrode is connected to the bonding area. The semiconductor device may have a multi-layer wiring structure, and the electrode pad connected to the multi-layer wiring structure. An uppermost wiring layer of the multi-layer wiring structure may be arranged in a region other than a region directly under the test probe area.

Claims

1. A semiconductor device comprising a plurality of I/O regions provided in a peripheral region of said semiconductor device,

wherein each of said plurality of I/O regions comprises an electrode pad,

said electrode pad has a test probe area and a bonding area which are separately provided, and

a test probe is made to contact said test probe area and an external electrode is connected to said bonding area, and

said test probe area is defined based on probe area markers that are protrusions extending in a direction from said electrode pad to an adjacent said electrode pad.

2. The semiconductor device according to claim 1, wherein said electrode pad has a 2-layer structure of an upper pad and a lower pad connected with said upper pad.

3. The semiconductor device according to claim 2, wherein said probe area markers are provided for said lower pad.

4. The semiconductor device according to claim 3, wherein two of said probe area markers are provided for a specific side of said lower pad opposing to an external side of said semiconductor device, and two of said probe area markers are provided for one of sides of said lower pad orthogonal to said specific side.

5. The semiconductor device according to claim 1, wherein said probe area markers are visible from above said semiconductor device.

6. A semiconductor device, comprising:

a plurality of I/O regions in a peripheral region of the semiconductor device;

an electrode pad in each of said plurality of I/O regions, said electrode pad having a bonding area and a test probe area entirely within said bonding area; and

two pairs of probe area markers that define said test probe area, one of said two pairs being outside a first peripheral side of said bonding area and a second of said two pairs being outside a second peripheral side of said bonding area orthogonal to said first peripheral side, each of said two pairs including two spaced apart marks that are respectively distinguishable from said first and second peripheral sides.

7. The device of claim 6, wherein said test probe area is closer to said first peripheral side than a third peripheral side of said bonding area opposite said first peripheral side and is closer to said second peripheral side than a fourth peripheral side of said bonding area opposite said second peripheral side.

8. The device of claim 6, wherein said electrode pad comprises an upper pad layer and a lower pad layer that are electrically connected to each other, wherein said lower pad layer has an extension that extends outside of said first peripheral side of said bonding area, and wherein said one of said two pairs is outside a distal peripheral edge of said extension.

9. A semiconductor device, comprising:

a plurality of I/O regions provided in a peripheral region of the semiconductor device, wherein,

each of said plurality of I/O regions comprises an electrode pad,

said electrode pad has a test probe area and a bonding area, the test probe area and the bonding area being separately provided,

with a test probe made to contact said test probe area and an external electrode connected to said bonding area, said test probe area is defined based on probe area markers, and said probe area markers are protrusions that are a part of said electrode pad.