Configurable IC's with logic resources with offset connections

• US 7,282,950 B1
• Filed: 03/15/2005
• Issued: 10/16/2007
• Est. Priority Date: 11/08/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Huang, Randy Renfu, Schmit, Herman, Teig, Steven, Hutchings, Brad
• Primary Examiner(s): Tan, Vibol
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/082,228
• Publication Number:
  US 20070241785A1
• Time in Patent Office: 945 Days
• Field of Search: 326 37- 41, 326/47, 716/16
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Claims

1. A configurable integrated circuit (“

IC”

) comprising;

a plurality of configurable tiles arranged in a tile arrangement,

each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits;

wherein at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement; and

wherein said direct connection does not include any intervening interconnect circuits.

2. The configurable IC of claim 1, wherein a plurality of logic circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

3. The configurable IC of claim 1, wherein the second circuit is a routing circuit.

4. The configurable IC of claim 3, wherein the second circuit receives output of the first circuit through the direct connection.

5. The configurable IC of claim 1, wherein the second circuit is a logic circuit.

6. The configurable IC of claim 1, wherein the second circuit receives output of the first circuit through the direct connection.

7. The configurable IC of claim 1 further comprising configurable input-select circuits for receiving and selecting inputs for configurable logic circuits, wherein the second circuit is a configurable input-select circuit that through the direct connection receives output of the first logic circuit.

8. The configurable IC of claim 1, wherein each of a plurality of logic circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.

9. The configurable IC of claim 1, wherein the direct connection does not include any intervening circuits.

10. The configurable IC of claim 9, wherein the direct connection includes a set of wire segments and a set of vias.

11. The configurable IC of claim 1, wherein the direct connection includes a set of wire segments and at least one intervening buffer circuit.

12. The configurable IC of claim 1, wherein the plurality of tiles includes at least 300 tiles.

13. The configurable IC of claim 1, wherein the plurality of tiles includes at least 1000 tiles.

14. An electronic device comprising:

a configurable integrated circuit (“

IC”

) comprising;

a) a plurality of configurable tiles arranged in a tile arrangement,

b) each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits;

c) wherein at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, and wherein said direct connection does not include any intervening interconnect circuits.

15. The electronic device of claim 14, wherein a plurality of logic circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

16. The electronic device of claim 14, wherein the second circuit is a routing circuit.

17. The electronic device of claim 16, wherein the second circuit receives output of the first circuit through the direct connection.

18. The electronic device of claim 14, wherein the second circuit is a logic circuit.

19. The electronic device of claim 14, wherein the second circuit receives output of the first circuit through the direct connection.

20. The electronic device of claim 14 further comprising configurable input-select circuits for receiving and selecting inputs for configurable logic circuits, wherein the second circuit is a configurable input-select circuit that through the direct connection receives output of the first logic circuit.

21. The electronic device of claim 14, wherein each of a plurality of logic circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.

22. A configurable integrated circuit (“

IC”

) comprising;

a plurality of configurable tiles arranged in a tile arrangement,

each particular tile having a set of configurable logic circuits, a set of configurable routing circuits for routing signals between configurable logic circuits, and a set of configurable input-select circuits for receiving inputs and configurably supplying a sub-set of the received inputs to the configurable logic circuits in the particular tile;

wherein at least a first input select circuit of a first tile has at least one direct connection with a second logic circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, wherein the direct connection is for supplying a signal to the first input select circuit, and wherein said direct connection does not include any intervening interconnect circuits.

23. The configurable IC of claim 22, wherein a plurality of input select circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

24. The configurable IC of claim 22, wherein the second logic circuit is a look up table.

25. The configurable IC of claim 22, wherein the second logic circuit is a three input logic circuit.

26. The configurable IC of claim 22, wherein each of a plurality of input select circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.

27. The configurable IC of claim 22, wherein the plurality of tiles includes at least 300 tiles.

28. The configurable IC of claim 22, wherein the plurality of tiles includes at least 1000 tiles.

29. An electronic device comprising:

a configurable integrated circuit (“

IC”

) comprising;

a plurality of configurable tiles arranged in a tile arrangement,

each particular tile having a set of configurable logic circuits, a set of configurable routing circuits for routing signals between configurable logic circuits, and a set of configurable input-select circuits for receiving inputs and configurably supplying a sub-set of the received inputs to the configurable logic circuits in the particular tile;

wherein at least a first input select circuit of a first tile has at least one direct connection with a second logic circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, wherein the direct connection is for supplying a signal to the first input select circuit, and wherein said direct connection does not include any intervening interconnect circuits.

30. The electronic device of claim 29, wherein a plurality of input select circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

31. The electronic device of claim 29, wherein the second logic circuit is a look up table.

32. The electronic device of claim 29, wherein the second logic circuit is a three input logic circuit.

33. The electronic device of claim 29, wherein each of a plurality of input select circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.