Active load with adjustable common-mode level

• US 7,282,994 B2
• Filed: 07/14/2005
• Issued: 10/16/2007
• Est. Priority Date: 10/14/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gopinathan, Venugopal, Galal, Sherif Hassan
• Primary Examiner(s): Choe; Henry
• Application Number:
  US11/180,678
• Publication Number:
  US 20060082415A1
• Time in Patent Office: 824 Days
• Field of Search: 330/253, 330/257, 330/258, 330/310, 330/311, 330/98, 330/150
• US Class Current: 330/253
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2203/45652 the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier

Abstract

A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.

Claims

1. A differential amplifier, comprising:

a first stage configured to receive a differential input signal; and

a second stage, coupled to an output of the first stage, including;

an active load having a transistor pair that provides a differential output signal at respective output terminals of the active load; and

a bias circuit that provides bias voltages to the transistor pair in the active load, and configured to provide an adjustable common-mode voltage at respective output terminals of the active load.

2. The differential amplifier of claim 1, wherein the transistor pair has their gates connected together at a common node, the bias circuit further comprising:

a current source coupled to the common node;

a first resistor coupled between a gate and a drain of a first transistor of the transistor pair, and a second resistor coupled between a gate and a drain of a second transistor of the transistor pair.

3. The differential amplifier of claim 2, wherein the current source is determined so that respective voltage drops across the first and second resistors provide a desired common-mode voltage at the output terminals of the active load.

4. The differential amplifier of claim 3, wherein the current source is determined so that respective voltage drops across the first and second resistors place the transistor pair in saturation.

5. The differential amplifier of claim 3, wherein the current source is determined by a feedback loop system coupled to the output terminals of the active load.

6. The differential amplifier of claim 5, wherein the feedback loop system monitors the common-mode voltage at the output terminals of the active load and generates an output signal to adjust the current source.

7. The differential amplifier of claim 1, wherein the transistor pair in the active load is a PMOS transistor pair.

8. A differential amplifier, comprising:

a first transistor pair configured to receive a differential input signal; and

an active load, coupled to the first transistor pair, including;

a second transistor pair that provides a differential output signal at respective output terminals of the active load; and

a bias circuit that provides bias voltages to the second transistor pair, and configured to provide an adjustable common-mode voltage at respective output terminals of the active load.

9. The differential amplifier of claim 8, wherein the second transistor pair has their gates connected together at a common node, the bias circuit further comprising:

a current source coupled to the common node;

a first resistor coupled between a gate and a drain of a first transistor of the second transistor pair, and a second resistor coupled between a gate and a drain of a second transistor of the second transistor pair.

10. The differential amplifier of claim 8, wherein the current source is determined so that respective voltage drops across the first and second resistors provide a desired common-mode voltage at the output terminals of the active load.

11. The differential amplifier of claim 10, wherein the current source is determined so that respective voltage drops across the first and second resistors place the second transistor pair in saturation.

12. The differential amplifier of claim 10, wherein the current source is determined by a feedback loop system coupled to the output terminals of the active load.

13. The differential amplifier of claim 12, wherein the feedback loop system monitors the common-mode voltage at the output terminals of the active load and generates an output signal to adjust the current source.

14. The differential amplifier of claim 8, wherein the first transistor pair is a NMOS transistor pair and the second transistor pair is a PMOS transistor pair.

15. In a differential amplifier having an active load, the active load including a first resistor coupled between a common node and a first output terminal of the active load and a second resistor coupled between the common node and a second output terminal of the active load, a method of providing an adjustable common-mode voltage at the respective output terminals of the active load, the method comprising the steps of:

(a) biasing the active load using a current source coupled to the active load at the common node; and

(b) adjusting the current source to provide desired voltage drops across the first and second resistors, wherein respective voltage drops across the first and second resistors provide the adjustable common-mode voltage at the output terminals of the active load.

16. The method of claim 15, further comprising the step of receiving a differential signal at an input transistor pair of the differential amplifier.

17. The method of claim 16, further comprising the step of amplifying the differential signal using the active load.

18. The method of claim 17, further comprising the step of outputting an amplified differential signal at the respective output terminals of the active load.

19. The method of claim 15, further comprising the step of outputting the common-mode voltage at the output terminals of the active load to drive a follow-on circuit.

20. The method of claim 15, wherein the first resistor of the active load and the second resistor of the active load has their gates connected together at the common node.

21. The method of claim 20, wherein the input transistor pair is a NMOS transistor pair and the first resistor of the active load and the second resistor of the active load are PMOS transistors.

22. The method of claim 15, wherein step (e) includes adjusting the current source with a feedback loop system coupled to the output terminals of the active load.

23. The method of claim 22, wherein step (e) includes monitoring the common-mode voltage at the output terminals of the active load with the feedback loop system and generating an output signal to adjust the current source.

24. A two stage differential amplifier having active loads with adjustable common-mode output voltages, comprising:

a differential amplifier input and a differential amplifier output;

a first differential amplifier stage including a first transistor pair, respective sources of the first transistor pair connected to a first current supply, respective gates of the first transistor pair connected to the differential amplifier input, respective drains of the first transistor pair connected to a first active load;

a second differential amplifier stage including a second transistor pair, respective sources of the second transistor pair connected to a second current supply, respective gates of the second transistor pair connected to the respective drains of the first transistor pair and forming a first differential amplifier stage output, respective drains of the second transistor pair connected to a second active load; and

a feedback resistor pair connecting the respective gates of the second transistor pair to the respective drains of the second transistor pair;

wherein;

the first active load includes a third transistor pair and a first active load resistor pair, respective sources of the third transistor pair connected to a first supply voltage, respective drains of the third transistor pair connected to the respective drains of the first transistor pair, respective gates of the third transistor pair connected to a third current source, the first active load resistor pair connecting the respective gates of the third transistor pair to the respective drains of the third transistor pair;

the second active load includes a fourth transistor pair and a second active load resistor pair, respective sources of the fourth transistor pair connected to a second supply voltage, respective drains of the fourth transistor pair connected to the respective drains of the second transistor pair, respective gates of the fourth transistor pair connected to a fourth current source, the second active load resistor pair connecting the respective gates of the fourth transistor pair to the respective drains of the fourth transistor pair; and

the differential amplifier output is taken from the drains of the fourth transistor pair.

25. The two stage differential amplifier of claim 24, wherein the first transistor pair and second transistor pair are NMOS transistors and the third transistor pair and fourth transistor pair are PMOS transistors.

26. The two stage differential amplifier of claim 24, wherein the third current source is adjusted to set a first common-mode output voltage at the first differential amplifier stage output and the fourth current source is adjusted to set a second common-mode output voltage at the differential amplifier output.

27. The two stage differential amplifier of claim 26, wherein the second common-mode output voltage is used to drive a follow-on circuit.

28. The two stage differential amplifier of claim 26, wherein the third current source is adjusted to place the third transistor pair in saturation and the fourth current source is adjusted to place the fourth transistor pair in saturation.

29. The two stage differential amplifier of claim 24, wherein a feedback loop system, having inputs connected to the differential amplifier output and an output connected to the fourth current source, monitors the second common-mode output voltage and adjusts the fourth current source.

30. A differential amplifier having an active load with adjustable common-mode output voltage, comprising:

a differential amplifier input and a differential amplifier output; and

a first transistor pair, respective sources of the first transistor pair connected to a first current supply, respective gates of the first transistor pair connected to the differential amplifier input, respective drains of the first transistor pair connected to an active load;

wherein;

the active load includes a second transistor pair and an active load resistor pair, respective sources of the second transistor pair connected to a first supply voltage, respective drains of the second transistor pair connected to the respective drains of the first transistor pair, respective gates of the second transistor pair connected to a second current source, the active load resistor pair connecting the respective gates of the second transistor pair to the respective drains of the second transistor pair; and

the differential amplifier output is taken from the drains of the second transistor pair.