Divide-add circuit and high-resolution digital-to-analog converter using the same
First Claim
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1. A divide-add circuit, comprising:
- a first capacitor configured to store charges depending on a first voltage across the first capacitor;
a third capacitor configured to store charges depending on a second voltage across the third capacitor;
a first path control switch connected to the third capacitor, and configured such that the first and third capacitors are connected in series to each other therethrough; and
a second capacitor connected in parallel to the first capacitor with respect to the first voltage, and configured to be connected in series to the third capacitor though the first path control switch;
wherein a value of voltage, which is obtained by dividing the second voltage at an appropriate ratio that is proportional to a ratio of the second and third capacitors, is added to the first voltage, prior to connection between the second and third capacitors; and
wherein a value of the first voltage across the first capacitor is calculated by a division and addition operation in a state in which the second capacitor is connected in series to the third capacitor through the first path control switch and the first and third capacitors are connected in parallel to each other.
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Abstract
Disclosed herein is a divide-add circuit and a high-resolution Digital-to-Analog Converter (DAC) using the same. The DAC includes a plurality of DAC units and one or more divide-add circuit units. The plurality of DAC units performs Digital-Analog (DA) conversion on two or more segmented codes, into which an input digital code is segmented. The one or more divide-add circuit units is configured to be each composed only of capacitors and switches and to generate a final DA conversion output for the entire input digital code based on the voltages of the DAC units. Accordingly, a high resolution of more than ten bits can be implemented.
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Citations
19 Claims
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1. A divide-add circuit, comprising:
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a first capacitor configured to store charges depending on a first voltage across the first capacitor; a third capacitor configured to store charges depending on a second voltage across the third capacitor; a first path control switch connected to the third capacitor, and configured such that the first and third capacitors are connected in series to each other therethrough; and a second capacitor connected in parallel to the first capacitor with respect to the first voltage, and configured to be connected in series to the third capacitor though the first path control switch; wherein a value of voltage, which is obtained by dividing the second voltage at an appropriate ratio that is proportional to a ratio of the second and third capacitors, is added to the first voltage, prior to connection between the second and third capacitors; and wherein a value of the first voltage across the first capacitor is calculated by a division and addition operation in a state in which the second capacitor is connected in series to the third capacitor through the first path control switch and the first and third capacitors are connected in parallel to each other. - View Dependent Claims (2, 3)
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4. A high-resolution Digital-to-Analog Converter (DAC) using a divide-add circuit, comprising:
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a plurality of DAC units for performing Digital-Analog (DA) conversion on two or more segmented codes, into which an input digital code is segmented; and at least one divide-add circuit unit to generate a final DA conversion output for the entire input digital code based on the voltages of the DAC units, each of said at least one divide-add circuit units consisting of capacitors and switches. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11)
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12. A high-resolution Digital-to-Analog Converter (DAC) using a divide-add circuit, comprising:
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a plurality of DAC units for performing Digital-Analog (DA) conversion on two or more segmented codes, into which an input digital code is segmented; and one or more divide-add circuit units configured to be each composed only of capacitors and switches and to generate a final DA conversion output for the entire input digital code based on the voltages of the DAC units, wherein the one or more divide-add circuit units are a plurality of divide-add circuit units that adds conversion results of the DAC units that perform DA conversion on the segmented codes, ranging from a segmented code including a Least Significant Bit (LSB) of the input digital code to a segmented code including a Most Significant Bit (MSB) of the input digital code, and obtains a DA conversion result of the entire input digital code. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification