Pipelined analog-to-digital converter with mid-sampling comparison

• US 7,283,083 B1
• Filed: 08/05/2005
• Issued: 10/16/2007
• Est. Priority Date: 08/05/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Aude, Arlo, Kamal, Abu-Hena Mostafa
• Primary Examiner(s): Mai; Lam T.
• Application Number:
  US11/161,502
• Time in Patent Office: 802 Days
• Field of Search: 341130-170
• US Class Current: 341/161
• CPC Class Codes: H03M 1/0624 by synchronisation
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/164 the steps being performed sequentially in series-connected stages H03M1/161 takes precedence
• CPC Class Codes: H03M 1/168 and delivering the same number of bits
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

A double-sampled pipeline analog-to-digital conversion (ADC) system and method in which latching of the intrastage digital quantization signals occurs approximately midway the leading and trailing edges of the clock signals.

Claims

1. An apparatus including double-sampled pipeline analog-to-digital conversion (ADC) circuitry having a plurality of serially coupled 1.5 bit ADC stages, comprising:

at least one electrode to convey an upstream residue signal from an upstream ADC stage;

residue signal generation circuitry coupled to said at least one electrode and responsive to said upstream residue signal, an analog quantization signal, a reset control signal and a first portion of a plurality of clock signals by providing a downstream residue signal;

sub-ADC circuitry coupled to said at least one electrode and responsive to said upstream residue signal and a latch control signal by providing first and second digital quantization signals;

digital-to-analog conversion (DAC) circuitry coupled to said sub-ADC circuitry and said residue signal generation circuitry, and responsive to said first and second digital quantization signals by providing said analog quantization signal; and

timing and control circuitry coupled to said residue signal generation circuitry and said sub-ADC circuitry, and responsive to at least a main clock signal by providing said reset control signal, said first portion of said plurality of clock signals and said latch control signal, wherein each one of said first portion of said plurality of clock signals includes respective leading and trailing signal state transitions, said latch control signal includes leading and trailing signal state transitions, and at least one of said leading and trailing latch control signal state transitions occurs approximately midway said leading and trailing clock signal state transitions.

2. The apparatus of claim 1, wherein said residue signal generation circuitry comprises sample and hold circuitry responsive to said first portion of said plurality of clock signals by sampling said upstream residue signal and summing said analog quantization signal therewith to provide said downstream residue signal.

3. The apparatus of claim 1, wherein said sub-ADC circuitry comprises:

comparator circuitry responsive to said upstream residue signal and a plurality of reference signals by providing a plurality of difference signals indicative of differences between said upstream residue signal and respective ones of said plurality of reference signals; and

latch circuitry coupled to said comparator circuitry and responsive to said latch control signal by latching said plurality of difference signals to provide said first and second digital quantization signals.

4. The apparatus of claim 1, wherein said timing and control circuitry comprises:

clock generator circuitry responsive to at least said main clock signal by providing said plurality of clock signals and an intermediate control signal;

latch control circuitry coupled to said clock generator circuitry and responsive to said intermediate control signal and a second portion of said plurality of clock signals by providing said latch control signal; and

reset control circuitry coupled to said clock generator circuitry and responsive to a third portion of said plurality of clock signals by providing said reset control signal.

5. The apparatus of claim 1, further comprising timing alignment circuitry coupled to said timing and control circuitry and responsive to said first and second digital quantization signals and said reset control signal by selectively combining and latching said first and second digital quantization signals to provide corresponding first and second latched quantization signals in synchronization with said reset control signal.

6. An apparatus including double-sampled pipeline analog-to-digital conversion (ADC) circuitry having a plurality of serially coupled 1.5 bit ADC stages, comprising:

residue signal generator means for receiving an upstream residue signal from an upstream ADC stage, an analog quantization signal, a reset control signal and a first portion of a plurality of clock signals and in response thereto generating a downstream residue signal;

sub-ADC means for receiving said upstream residue signal and a latch control signal and in response thereto generating first and second digital quantization signals;

digital-to-analog conversion (DAC) means for receiving said first and second digital quantization signals and in response thereto generating said analog quantization signal; and

timing and control means for receiving at least a main clock signal and in response thereto generating said reset control signal, said first portion of said plurality of clock signals and said latch control signal, wherein each one of said first portion of said plurality of clock signals includes respective leading and trailing signal state transitions, said latch control signal includes leading and trailing signal state transitions, and at least one of said leading and trailing latch control signal state transitions occurs approximately midway said leading and trailing clock signal state transitions.

7. The apparatus of claim 6, further comprising timing alignment means for receiving said first and second digital quantization signals and said reset control signal and in response thereto selectively combining and latching said first and second digital quantization signals to provide corresponding first and second latched quantization signals in synchronization with said reset control signal.

8. A method of performing double-sampled pipeline analog-to-digital conversion (ADC) of a signal with a plurality of serially coupled 1.5 bit ADC stages, comprising:

receiving an upstream residue signal from an upstream ADC stage;

receiving an analog quantization signal;

receiving a reset control signal;

receiving a first portion of a plurality of clock signals;

receiving a latch control signal;

receiving at least a main clock signal;

generating a downstream residue signal in response to said upstream residue signal, said analog quantization signal, said reset control signal and said first portion of a plurality of clock signals;

generating first and second digital quantization signals in response to said upstream residue signal and said latch control signal;

generating said analog quantization signal in response to said first and second digital quantization signals; and

generating said reset control signal, said first portion of said plurality of clock signals and said latch control signal in response to at least said main clock signal;

wherein each one of said first portion of said plurality of clock signals includes respective leading and trailing signal state transitions, said latch control signal includes leading and trailing signal state transitions, and at least one of said leading and trailing latch control signal state transitions occurs approximately midway said leading and trailing clock signal state transitions.

9. The method of claim 8, wherein said generating a downstream residue signal in response to said upstream residue signal, said analog quantization signal, said reset control signal and said first portion of a plurality of clock signals comprises sampling said upstream residue signal in response to said first portion of said plurality of clock signals and summing said analog quantization signal therewith to produce said downstream residue signal.

10. The method of claim 8, wherein said generating first and second digital quantization signals in response to said upstream residue signal and said latch control signal comprises:

receiving a plurality of reference signals;

comparing said upstream residue signal and respective ones of said plurality of reference signals and in response thereto generating a plurality of difference signals indicative of differences between said upstream residue signal and said respective ones of said plurality of reference signals; and

latching said plurality of difference signals in response to said latch control signal to produce said first and second digital quantization signals.

11. The method of claim 8, wherein said generating said reset control signal, said first portion of said plurality of clock signals and said latch control signal in response to at least said main clock signal comprises:

generating said plurality of clock signals and an intermediate control signal in response to at least said main clock signal;

generating said latch control signal in response to said intermediate control signal and a second portion of said plurality of clock signals; and

generating said reset control signal in response to a third portion of said plurality of clock signals.

12. The method of claim 8, further comprising selectively combining and latching said first and second digital quantization signals in response to said first and second digital quantization signals and said reset control signal to produce corresponding first and second latched quantization signals in synchronization with said reset control signal.