Memory device and method for simultaneously programming and/or reading memory cells on different levels

• US 7,283,403 B2
• Filed: 11/12/2004
• Issued: 10/16/2007
• Est. Priority Date: 11/16/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Johnson, Mark G.
• Primary Examiner(s): Le; Thong Q.
• Application Number:
  US10/987,091
• Publication Number:
  US 20050063220A1
• Time in Patent Office: 1,068 Days
• Field of Search: 365/189.04, 365/230.06
• US Class Current: 365/189.04
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A memory device comprising:

a three-dimensional memory array comprising;

a first level of memory cells;

a second level of memory cells; and

a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and

circuitry operative to simultaneously program at least two memory cells, at least one in the first level and at least one in the second level.

2. The memory device of claim 1, wherein the first level of memory cells and the second level of memory cells are built over a silicon substrate.

3. The memory device of claim 1, wherein the memory cells in the first and second levels comprise write-once memory cells.

4. The memory device of claim 1, wherein the memory cells in the first and second levels comprise write-many memory cells.

5. The memory device of claim 1 further comprising:

circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level.

6. A memory device comprising:

a first level of memory cells;

a second level of memory cells;

circuitry operative to simultaneously program at least two memory cells, at least one in the first level and at least one in the second level; and

a plurality of conductor layers, wherein the first and second levels of memory cells are between the plurality of conductor layers;

wherein the plurality of conductor layers comprises first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layer; and

wherein the first, second, and third conductor layers each comprise a respective plurality of conductor lines, and wherein the conductor lines of the first conductor layer are perpendicular to the conductor lines of the second conductor layer, and wherein the conductor lines of the second conductor layer are perpendicular to the conductor lines of the third conductor layer.

7. A memory device comprising:

a three-dimensional memory array comprising;

a first level of memory cells;

a second level of memory cells; and

a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and

circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level.

8. The memory device of claim 7, wherein the first level of memory cells and the second level of memory cells are built over a silicon substrate.

9. The memory device of claim 7, wherein the memory cells in the first and second levels comprise write-once memory cells.

10. The memory device of claim 7, wherein the memory cells in the first and second levels comprise write-many memory cells.

11. A memory device comprising:

a first level of memory cells;

a second level of memory cells;

circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level; and

a plurality of conductor layers, wherein the first and second levels of memory cells are between the plurality of conductor layers;

wherein the plurality of conductor layers comprises first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and

wherein the first, second, and third conductor layers each comprise a respective plurality of conductor lines, and wherein the conductor lines of the first conductor layer are perpendicular to the conductor lines of the second conductor layer, and wherein the conductor lines of the second conductor layer are perpendicular to the conductor lines of the third conductor layer.

12. A method comprising:

with a memory device comprising first and second levels of memory cells and a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers, performing at least one of the following;

(a) simultaneously programming at least two memory cells, at least one in the first level and at least one in the second level; and

(b) simultaneously reading at least two memory cells, at least one in the first level and at least one in the second level.

13. The method of claim 12, wherein the first level of memory cells and the second level of memory cells are built over a silicon substrate.

14. The method of claim 12, wherein the memory cells in the first and second levels comprise write-once memory cells.

15. The method of claim 12, wherein the memory cells in the first and second levels comprise write-many memory cells.

16. A method comprising:

(a) providing a memory device comprising first and second levels of memory cells; and

(b) performing at least one of the following;

(b1) simultaneously programming at least two memory cells, at least one in the first level and at least one in the second level; and

(b2) simultaneously reading at least two memory cells, at least one in the first level and at least one in the second level;

wherein the memory device further comprises a plurality of conductor layers, wherein the first and second levels of memory cells are between the plurality of conductor layers;

wherein the plurality of conductor layers comprises first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and

wherein the first, second, and third conductor layers each comprise a respective plurality of conductor lines, and wherein the conductor lines of the first conductor layer are perpendicular to the conductor lines of the second conductor layer, and wherein the conductor lines of the second conductor layer are perpendicular to the conductor lines of the third conductor layer.

17. A memory device comprising:

a first level of memory cells;

a second level of memory cells;

a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers;

circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level; and

a plurality of sense amplifiers, one sense amplifier for each of the at least two memory cells.

18. A method comprising:

with a memory device comprising first and second levels of memory cells and a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers, performing at least one of the following;

(a) simultaneously programming at least two memory cells, at least one in the first level and at least one in the second level; and

(b) simultaneously reading at least two memory cells, at least one in the first level and at least one in the second level;

wherein the at least two memory cells are simultaneously read in (b) using a plurality of sense amplifiers, one sense amplifier for each of the at least two memory cells.