Real-time adaptive SRAM array for high SEU immunity

• US 7,283,410 B2
• Filed: 03/13/2006
• Issued: 10/16/2007
• Est. Priority Date: 03/13/2006
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Chih-Chao, Wong, Robert C., Hsu, Louis L., Mandelman, Jack A.
• Primary Examiner(s): Nguyen; Tuan T.
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US11/308,215
• Publication Number:
  US 20070211527A1
• Time in Patent Office: 582 Days
• Field of Search: 365/201, 714/42
• US Class Current: 365/201
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information

Abstract

A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

Claims

1. A method for adapting sensitivity of a memory device to single event upsets (SEUs) due to ionizing particles, said method comprising:

providing a first memory device adapted for receiving single event upsets due to ionizing particles;

generating fail rate data at said first memory device;

providing a control device for receiving said fail rate data input from the first memory device;

determining a predetermined SEU fail rate for said second memory device;

dynamically applying voltage biases to a second memory device, said voltage biases optimally mapped according to said predetermined SEU fail rate,

wherein an operating point for said second memory device is dynamically achieved that balances SEU immunity and memory device performance.

2. The method according to claim 1, wherein said first and second memory devices include a SRAM having nMOS FET and PMOS FET devices.

3. The method according to claim 2, wherein said voltage level settings are applied to one or more of:

an N-well supply voltage (Vnw), a P-well supply voltage (Vpw), and a supply voltage Vdd, said voltage level settings of Vnw, Vdd, Vpw set to meet said predetermined SEU fail rate.

4. The method according to claim 3, wherein said first memory device adapted for receiving single event upsets is programmed with voltage biases levels to provide an accelerated SEU failure rate.

5. The method according to claim 4, further including providing a worst case bias setting on said first memory array to achieve said accelerated SEU failure rate.

6. The method according to claim 3, wherein said accelerated SEU failure rate is achieved by operating said first memory device with a high back bias (Vpw) on the NFET transfer devices, high N-well bias (Vnw) on the PFET pull-up devices, or low power supply voltage (Vdd).

7. The method according to claim 3, wherein said determining a predetermined SEU fail rate for said second memory device comprises:

comparing fail rate data generated by said first memory device with pre-programmed data describing dependence of bit fail rate of the second memory device to the N-well supply voltage (Vnw), P-well supply voltage (Vpw) and a device supply voltage Vdd.

8. The method according to claim 7, wherein said determining a predetermined SEU fail rate comprises:

converting said fail rate data generated by said first memory device to a nominal fail rate value representing a failure rate with nominal bias in a given physical environment;

comparing said nominal fail rate value against a pre-programmed value indicating a maximum failure rate allowed for said given physical environment; and

,

calculating a soft error margin value representing the difference between the maximum allowed failure rate value and said nominal fail rate value.

9. The method according to claim 8, further including:

mapping said calculated soft error margin value to optimal voltage bias settings for said second memory device.

10. A system for adapting sensitivity of a memory device to single event upsets (SEUs) due to ionizing particles, said system comprising:

a first memory array adapted to receive single event upsets due to ionizing particles, said first memory array providing fail rate data;

a control device for receiving said fail rate data input from the first sensing memory array and determining a predetermined SEU fail rate for said second memory device, said control device further generating signals adapted for use in setting voltages voltage biases for said second memory device according to said predetermined SEU fail rate; and

,

means responsive to said signals for dynamically applying voltage biases to said second memory device,

wherein an operating point for said second memory device is dynamically achieved that balances SEU immunity and memory device performance.

11. The system according to claim 10, wherein said first and second memory devices include a SRAM having nMOS FET and PMOS FET devices.

12. The system according to claim 11, wherein said voltage level settings are applied to one or more of:

an N-well supply voltage (Vnw), a P-well supply voltage (Vpw), and a supply voltage Vdd, said voltage level settings of Vnw, Vdd, Vpw set to meet said predetermined SEU fail rate.

13. The system according to claim 12, further comprising means for applying said first memory device with voltage biases levels to provide an accelerated SEU failure rate.

14. The system according to claim 13, wherein said applying means provides a worst case bias setting on said first memory array to achieve said accelerated SEU failure rate.

15. The system according to claim 12, wherein said accelerated SEU failure rate is achieved by operating said first memory device with a large back bias (Vpw) on the NFET transfer devices, large N-well bias (Vnw) on the PFET pull-up devices, or low power supply voltage (Vdd).

16. The system according to claim 12, wherein said control device determines a predetermined SEU fail rate for said second memory device by:

comparing fail rate data generated by said first memory device with pre-programmed data describing dependence of bit fail rate of the second memory device to the N-well supply voltage (Vnw), P-well supply voltage (Vpw) and a device supply voltage Vdd.

17. The system according to claim 16, wherein said determining a predetermined SEU fail rate comprises:

converting said fail rate data generated by said first memory device to a nominal fail rate value representing a failure rate with nominal bias in a given physical environment;

comparing said nominal fail rate value against a pre-programmed value indicating a maximum failure rate allowed for said given physical environment;

calculating a soft error margin value representing the difference between the maximum allowed failure rate value and said nominal fail rate value; and

,

mapping said calculated soft error margin value to optimal voltage bias settings for said second memory device.

18. The system according to claim 10, wherein said first and second memory devices comprise SRAM cells built on an SOI substrate.

19. The system according to claim 10, wherein said first and second memory devices comprise SRAM cells built on a bulk substrate having a triple-well structure.

20. The system according to claim 10, wherein said means responsive to said signals for dynamically applying voltage biases to said second memory device comprise one or more charge control pump devices.