Write control circuitry and method for a memory array configured with multiple memory subarrays

• US 7,283,417 B2
• Filed: 02/09/2005
• Issued: 10/16/2007
• Est. Priority Date: 02/09/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Plass, Donald W., Davis, John D., Bunce, Paul A., Reyer, Kenneth J.
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Graham; Kretelia
• Application Number:
  US11/054,059
• Publication Number:
  US 20060176756A1
• Time in Patent Office: 979 Days
• Field of Search: 365/230.03, 365/154, 365/156
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

Claims

1. Write control circuitry for a memory array configured with multiple memory subarrays, the write control circuitry comprising:

multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to one associated memory subarray of the multiple memory subarrays, wherein the selectively enabling comprises outpuffing a write enable signal to the associated memory subarray, and wherein at least some subarray write controllers of the multiple subarray write controllers are powered at least in part via a switched power node, and wherein the switched power node is driven by multiple drivers distributively implemented among the multiple subarray write controllers associated with the multiple memory subarrays;

a plurality of subarray select signals, only one subarray select signal being active at a time, and wherein each subarray select signal drives a different subarray write controller of the multiple subarray write controllers, resulting in only one write enable signal being output from one subarray write controller to its associated memory subarray at a time; and

wherein the multiple subarray write controllers comprise local bitline write control circuits, each local bitline write control circuit comprising a buffer circuit having two series connected inverters, wherein a first inverter in the series is smaller than a second inverter in the series, and wherein the smaller inverter is powered by the switched power node.

2. The write control circuitry of claim 1, wherein the distributively implemented drivers driving the switched power node comprise multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal, wherein the multiple inverters power the switched power node responsive to the global write enable signal.

3. The write control circuitry of claim 2, wherein each inverter comprises a PFET and NFET pair coupled between a supply voltage Vdd and ground, with commonly connected gates receiving the global write enable signal, and commonly coupled drains connected to the switched power node.

4. The write control circuitry of claim 2, wherein the multiple inverters are implemented in multiple separate available spaces of the subarray write controllers.

5. The write control circuitry of claim 1, further comprising a plurality of subarray select signals, only one subarray select signal being active at a time, and wherein each subarray select signal drives both a subarray row decoder and a subarray write controller for the associated memory subarray, the subarray write controller comprising one write controller of the multiple subarray write controllers.

6. An apparatus comprising:

a memory array configured with multiple memory subarrays, each memory subarray being accessed via a respective subarray select signal; and

multiple subarray write controllers, each subarray write controller being associated with one memory subarray of the multiple memory subarrays, and wherein each subarray write controller selectively enables a local write control signal to its associated memory subarray responsive to a received subarray select signal, and wherein at least some subarray write controllers of the multiple subarray write controllers are powered at least in part via a switched power node, and wherein the switched power node is driven by multiple drivers distributively implemented among the multiple subarray write controllers associated with the multiple memory subarrays;

wherein the distributively implemented drivers driving the switched power node comprise multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal, wherein the multiple inverters power the switched power node responsive to the global write enable signal and

wherein each inverter comprises a PFET and NFET pair coupled between a supply voltage Vdd and ground, with commonly connected gates receiving the global write enable signal, and commonly coupled drains connected to the switched power node.

7. The apparatus of claim 6, wherein only one subarray select signal is active at a time, and wherein each subarray select signal drives a different subarray write controller of the multiple subarray write controllers, resulting in only one write enable signal being output from one subarray write controller to its associated memory subarray at a time.

8. The apparatus of claim 7, wherein the multiple subarray write controllers comprise local bitline write control circuits, each local bitline write control circuit comprising a buffer circuit having two series connected inverters, wherein a first inverter in the series is smaller than a second inverter in the series, and wherein the smaller inverter is powered by the switched power node.

9. The apparatus of claim 6, wherein the multiple inverters are implemented in multiple separate available spaces of the subarray write controllers.

10. The apparatus of claim 6, further comprising a plurality of subarray select signals, only one subarray select signal being active at a time, and wherein each subarray select signal drives both a subarray row decoder and a subarray write controller for the associated memory subarray, the subarray write controller comprising one write controller of the multiple subarray write controllers.

11. A write control method for a memory array configured with multiple memory subarrays, the method comprising:

selectively enabling a local write control signal to one memory subarray of the multiple memory subarrays at a time, each memory subarray having an associated subarray write controller, wherein the selectively enabling comprises allowing one subarray write controller at a time to output a write enable signal to its associated memory subarray, at least some subarray write controllers of the associated subarray write controllers being powered at least in part via a switched power node, wherein the switched power node is driven by multiple drivers distributively implemented among the subarray write controllers associated with the memory subarrays;

gating each subarray write controller with a different subarray select signal of a plurality of subarray select signals, wherein only one subarray select signal is active at a time, resulting in only one write enable signal being output from one subarray write controller to its associated memory subarray at a time; and

wherein the associated subarray write controllers employed by the selectively enabling comprise local bitline write control circuits, each local bitline write control circuit comprising a buffer circuit having two series connected inverters, wherein a first inverter in the series is smaller than a second inverter in the series, and wherein the smaller inverter is powered by the switched power node.

12. The method of claim 11, wherein the distributively implemented drivers driving the switched power node comprise multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal, wherein the multiple inverters power the switched power node responsive to the global write enable signal.

13. The method of claim 12, wherein each inverter is a PFET and NFET pair coupled between a supply voltage Vdd and ground, with commonly connected gates receiving the global write enable signal, and commonly coupled drains connected to the switched power node.

14. The method of claim 13, wherein the multiple inverters are implemented in multiple separate available spaces of the subarray write controllers.