Apparatus and method to coordinate calendar searches in a network scheduler
First Claim
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1. A system including:
- a network processor;
a scheduler operatively connected within said network processor;
a timing subsystem operatively coupled to the scheduler, said timing subsystem including;
a search engine;
an array of calendars with outputs operatively coupled to inputs of said search engine;
a Winner Valid array operatively coupled to the calendar search engine;
a Winning Location array operatively coupled to the calendar search engine;
a Current Working Pointer array having outputs operatively coupled to the calendar search engine;
a controller responsive to received signals to generate control signals which put the timing subsystem in an initial state and causes the calendar search engine to search identified calendars and load results of searches into the Winner Valid Array and Winning Location Array within a predefined time interval; and
a final decision logic circuit arrangement operatively coupled to the Winning Location Array and the Winning Valid Array, wherein said final decision logic circuit arrangement parses information in said Winning Location Array and said Winning Valid Array to select one of the calendars as a Winner, selects a location in the Winner as Winning Location and generates a signal indicating the Winner and Winning Location are valid; and
wherein the network processor includes;
n flow queues, n>
1;
m port queues, m>
1; and
an embedded processor complex that routes packets into said flow queues wherein said scheduler is responsive to signals generated by the final decision logic circuit arrangement to cause the packets to be transported from the flow queues to the port queues.
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Abstract
A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array that is selected as a result of a search process being executed on a plurality of calendars in the calendar status array.
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Citations
19 Claims
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1. A system including:
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a network processor; a scheduler operatively connected within said network processor; a timing subsystem operatively coupled to the scheduler, said timing subsystem including; a search engine; an array of calendars with outputs operatively coupled to inputs of said search engine; a Winner Valid array operatively coupled to the calendar search engine; a Winning Location array operatively coupled to the calendar search engine; a Current Working Pointer array having outputs operatively coupled to the calendar search engine; a controller responsive to received signals to generate control signals which put the timing subsystem in an initial state and causes the calendar search engine to search identified calendars and load results of searches into the Winner Valid Array and Winning Location Array within a predefined time interval; and a final decision logic circuit arrangement operatively coupled to the Winning Location Array and the Winning Valid Array, wherein said final decision logic circuit arrangement parses information in said Winning Location Array and said Winning Valid Array to select one of the calendars as a Winner, selects a location in the Winner as Winning Location and generates a signal indicating the Winner and Winning Location are valid; and wherein the network processor includes; n flow queues, n>
1;m port queues, m>
1; andan embedded processor complex that routes packets into said flow queues wherein said scheduler is responsive to signals generated by the final decision logic circuit arrangement to cause the packets to be transported from the flow queues to the port queues. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system including:
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a network processor; a scheduler operatively connected within said network processor; and a timing subsystem operatively coupled to the scheduler, said timing subsystem including; a search engine; an array of calendars with outputs operatively coupled to inputs of said search engine; a Winner Valid array operatively coupled to the calendar search engine; a Winning Location array operatively coupled to the calendar search engine; a Current Working Pointer array having outputs operatively coupled to the calendar search engine; a controller responsive to received signals to generate control signals which put the timing subsystem in an initial state and causes the calendar search engine to search identified calendars and load results of searches into the Winner Valid Array and Winning Location Array within a predefined time interval; a time based search arrangement operable to search a first set of calendars within the array of calendars; a non-time based search arrangement operable to search a second set of calendars within the array of calendars; and a selector responsive to a selection type signal to select outputs from the time based search arrangement and non-time based search arrangement; and a final decision logic circuit arrangement operatively counted to the Winning Location Array and the Winning Valid Array, wherein said final decision logic circuit arrangement parses information in said Winning Location Array and said Winning Valid Array to select one of the calendars as a Winner, selects a location in the Winner as Winnine Location and generates a signal indicating the Winner and Winning Location are valid. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsRumph, Darryl J., Bullis, Bryan K.
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Primary Examiner(s)Kizou; Hassan
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Assistant Examiner(s)Ahmed; Salman
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Application NumberUS10/255,861Publication NumberTime in Patent Office1,846 DaysField of Search370412-418, 370/230.1US Class Current370/394CPC Class CodesG06Q 10/109 Time management, e.g. calen...
