Programmable data encryption engine

• US 7,283,628 B2
• Filed: 06/12/2002
• Issued: 10/16/2007
• Est. Priority Date: 11/30/2001
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Stein, Yosef, Primo, Haim
• Primary Examiner(s): Song; Hosuk
• Assistant Examiner(s): SHAW, YIN CHEN
• Application Number:
  US10/170,267
• Publication Number:
  US 20030103626A1
• Time in Patent Office: 1,952 Days
• Field of Search: 380 28- 29, 380/37, 380 42- 45, 380/46, 708/490, 708/492, 714/781, 714/763, 326 39- 40, 713/189
• US Class Current: 380/29
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

Abstract

A programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm includes a Galois field linear transformer system (GFLT) responsive to a first input data block to execute an E permutation to obtain an expanded data block and combine it with a key to obtain a second larger intermediate data block in one cycle; and further includes a parallel look-up table system for implementing the unique data encryption standard selection function(s) and for condensing the second larger intermediate data block to a third data block similar to the first input data block in a second cycle and submitting it to the Galois field linear transformer system to execute a second permutation in a third cycle resulting in a data encryption standard cipher function of the first input data block.

Claims

1. A programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm comprising:

a reconfigurable Galois field linear transformer (GFLT) system responsive to a first input data block to execute an expansion permutation to obtain an expanded data block and combine it with a key to obtain a second larger intermediate data block in one cycle the GFLT system including at least one Galois field linear transformer circuit that includes a matrix responsive to a number of input bits in one or more bit steams and has a plurality of outputs for providing the Galois field linear transformation of those bits;

said matrix including a plurality of cells, each of said cells including an exclusive OR logic circuit, a programmable storage device, and an output and two inputs, one of the inputs for each of said cells with the exception of a first cell responsive to the output of a previous cell, in which, depending on programming of the associated storage device, the output of each of said cells is a result of the exclusive OR function of the two inputs, or each of said cells is bypassed and the output of each of said cells is the output of the previous cell; and

a parallel look-up table system for implementing a unique data encryption standard (DES) selection function and for condensing said second larger intermediate data block to a third data block similar to said first input data block in a second cycle and submitting it to said Galois field linear transformer system to execute a second permutation in a third cycle resulting in a data encryption standard cipher function of the first input data block.

2. The programmable data encryption engine of claim 1 in which said Galois field linear transformer system includes a first Galois field linear transformer circuit responsive to said first input data block and a second Galois field linear transformer circuit responsive to said third data block from said parallel look-up system.

3. The programmable data encryption engine of claim 1 in which, each cell further includes an AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of said input bits, the programmable storage device providing an input to its associated AND logic circuit for setting the matrix to obtain a multicycle Galois field linear transformation of the inputs in a single cycle.

4. The programmable data encryption engine of claim 1 in which Galois field linear transformer system includes a reconfigurable input Galois field linear transformer circuit.

5. The programmable data encryption engine of claim 4 in which said reconfigurable input Galois field linear transformer circuit includes a Galois field linear transformer having a matrix of cells, a plurality of storage planes for storing control patterns representing a number of different functions, a storage plane selector circuit for selecting a said storage plane representing a said function for enabling the cells of said matrix which define that function, and a reconfigurable input circuit for delivering input data to said enabled cells to apply that function to the input data.

6. The programmable data encryption engine of claim 1 in which said parallel look-up table system includes a memory, a plurality of look-up tables stored in said memory, a row index register for holding the values to be looked up in said look-up tables, a column index register for storing a value representing the starting address of each said look-up table stored in said memory, and an address translation circuit responsive to said column index register and said row index register to simultaneously generate an address for each value in said row index register to locate in parallel the functions of those values in each look-up table.

7. The programmable data encryption engine of claim 1 further including a key generator system for selectively providing a plurality of keys to said Galois field linear transformer system.

8. The programmable data encryption engine of claim 7 in which said key generator system includes a key register for storing said keys.

9. The programmable data encryption engine of claim 8 in which said key generator system includes a key generator circuit responsive to a master key for generating said keys.

10. The programmable data encryption engine of claim 9 in which said key generator circuit includes a Galois field linear transformer circuit.

11. The programmable data encryption engine of claim 9 in which said key generator circuit is included in said Galois field linear transformer system.

12. The programmable data encryption engine of claim 1 in which said Galois field linear transformer system is a reconfigurable input Galois field linear transformer circuit with a plurality of storage planes, one associated with each of said permutations.

13. The programmable data encryption engine of claim 11 in which said Galois field linear transformer system includes a reconfigurable input Galois field linear transformer circuit and includes a storage plane for defining said key generator circuit.

14. The programmable data encryption engine of claim 1 in which said Galois field linear transformer system includes a set of key selector cells for combining said key with said expanded data block.

15. The programmable data encryption engine of claim 14 in which a said key selector cell includes a gate circuit for transmitting a data signal, and a latch circuit for selectively enabling said gate circuit to pass said data signal.

16. The programmable data encryption engine of claim 15 in which said latch circuit includes a flip-flop circuit.

17. The programmable data encryption engine of claim 15 in which said gate circuit includes a pair of AND gates and an OR gate.

18. The programmable data encryption engine of claim 15 in which said gate circuit includes a two to one mux circuit.

19. The programmable data encryption engine of claim 4 in which said reconfigurable input Galois field linear transformer system includes a storage plane for defining the initial permutation and the reverse initial permutation of the data encryption standard (DES) algorithm.

20. A programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm comprising:

a key generator system; and

a reconfigurable Galois field linear transformer (GFLT) system responsive to a first input data block to execute an expansion DES E permutation to obtain an expanded data block and combine it with a key from said key generator to obtain a second larger intermediate data block in one cycle the GFLT system including at least one Galois field linear transformer circuit that includes a matrix responsive to a number of input bits in one or more bit steams and has a plurality of outputs for providing the Galois field linear transformation of those bits;

said matrix including a plurality of cells, each of said cells including an exclusive OR logic circuit, a programmable storage device, and an output and two inputs, one of the inputs for each of said cells with the exception of a first cell responsive to the output of a previous cell, in which, depending on programming of the associated storage device, the output of each of said cells is a result of the exclusive OR function of the two inputs, or each of said cells is bypassed and the output of each of said cells is the output of the previous cell; and

a parallel look-up table system for implementing a unique data encryption standard (DES) selection function and for condensing said second larger intermediate data block to a third data block similar to said first input data block in a second cycle and submitting it to said Galois field linear transformer system to execute a second permutation in a third cycle resulting in a data encryption standard cipher function of the first input data block.

21. The programmable data encryption engine of claim 20 in which said Galois field linear transformer system includes a first Galois field linear transformer circuit responsive to said first input data block and a second Galois field linear transformer circuit responsive to said third data block from said parallel look-up system.

22. The programmable data encryption engine of claim 20 in which, each cell further includes an AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of said input bits, the programmable storage device providing an input to its associated AND logic circuit for setting the matrix to obtain a multicycle Galois field linear transformation of the inputs in a single cycle.

23. The programmable data encryption engine of claim 20 in which Galois field linear transformer system includes a reconfigurable input Galois field linear transformer circuit.

24. The programmable data encryption engine of claim 23 in which said reconfigurable input Galois field linear transformer circuit includes a Galois field linear transformer having a matrix of cells, a plurality of storage planes for storing control patters representing a number of different functions, a storage plane selector circuit for selecting a said storage plane representing a said function for enabling the cells of said matrix which define that function, and a reconfigurable input circuit for delivering input data to said enabled cells to apply that function to the input data.

25. The programmable data encryption engine of claim 20 in which said parallel look-up table system includes a memory, a plurality of look-up tables stored in said memory, a row index register for holding the values to be looked up in said look-up tables, a column index register for storing a value representing the starting address of each said look-up table stored in said memory, and an address translation circuit responsive to said column index register and said row index register to simultaneously generate an address for each value in said row index register to locate in parallel the functions of those values in each look-up table.

26. The programmable data encryption engine of claim 20 in which said key generator system includes a key register for storing said keys.

27. The programmable data encryption engine of claim 26 in which said key generator system includes a key generator circuit responsive to a master key for generating said keys.

28. The programmable data encryption engine of claim 27 in which said key generator circuit includes a Galois field linear transformer circuit.

29. The programmable data encryption engine of claim 27 in which said key generator circuit is included in said Galois field linear transformer system.

30. The programmable data encryption engine of claim 20 in which said Galois field linear transformer system is a reconfigurable input Galois field linear transformer circuit with a plurality of storage planes, one associated with each of said permutations.

31. The programmable data encryption engine of claim 29 in which said Galois field linear transformer system includes a reconfigurable input Galois field linear transformer circuit and includes a storage plane for defining said key generator circuit.

32. The programmable data encryption engine of claim 20 in which said Galois field linear transformer system includes a set of key selector cells for combining said keys with said expanded data block.

33. The programmable data encryption engine of claim 32 in which a said key selector cell includes a gate circuit for transmitting a data signal, and a latch circuit for selectively enabling said gate circuit to pass said data signal.

34. The programmable data encryption engine of claim 33 in which said latch circuit includes a flip-flop circuit.

35. The programmable data encryption engine of claim 34 in which said gate circuit includes a pair of AND gates and an OR gate.

36. The programmable data encryption engine of claim 34 in which said gate circuit includes a two to one mux circuit.

37. The programmable data encryption engine of claim 23 in which said reconfigurable input Galois field linear transformer circuit includes a storage plane for defining the initial permutation and the reverse initial permutation of the data encryption standard (DES) algorithm.