Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals

• US 7,283,801 B2
• Filed: 05/05/2003
• Issued: 10/16/2007
• Est. Priority Date: 05/27/2002
• Status: Expired due to Fees

• Current Assignee: Nokia Corporation
• Original Assignee: Nokia Corporation
• Inventors: Suhonen, Markus
• Primary Examiner(s): Urban; Edward F.
• Assistant Examiner(s): Hannon; Christian A.
• Application Number:
  US10/429,493
• Publication Number:
  US 20030220087A1
• Time in Patent Office: 1,625 Days
• Field of Search: 455/260, 4553431-3436
• US Class Current: 455/343.4
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/105 Resetting the controlled oscillator when its frequency is outside a predetermined limit
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

The invention relates to a circuit arrangement (4) for a PLL to be used in a terminal (50) of a time division cellular network. In a PLL according to the invention, the control voltage (32a) to a VCO (33) in the PLL is kept at a desired value also during time slots in which the terminal is not receiving or transmitting messages. The settling time for a PLL according to the invention is shot and the spurious effects caused by the power up thereof are small. The invention further relates to a method of operation for a PLL.

Claims

1. A circuit arrangement for implementing a PLL in a time-division cellular network terminal in which power supply to at least some of the circuit elements of the terminal is arranged to be switched off for the duration of time slots not used in data transfer, comprising:

means for receiving an external signal and processing it into a reference signal,

means for indicating a signal representing a phase difference between said processed reference signal and a comparable signal generated in the circuit arrangement,

means for producing, using said indicated signal, a voltage change proportional to the phase difference,

a voltage controlled oscillator (VCO), for producing, on the basis of said voltage change proportional to the phase difference, an output signal having a varying frequency, and

means for switching off power supply of the VCO in the PLL for the duration of time slots not used in data transfer,

in which circuit arrangement a power supply voltage is arranged to be connected to the means for producing a voltage change proportional to the phase difference also during time slots not used in data transfer in order to reduce the restart time and switching noise in the PLL, wherein the means for producing an output signal having a varying frequency comprise a VCO which is arranged to be controlled using a control voltage obtained from an output of a low-pass filter, and

wherein the initial value of the VCO control voltage obtained from an output of a low-pass filter is arranged to be set, at the end of each time slot used in data transfer, to a voltage value which is 100 to 200 mV above the VCO control voltage to be used in the next time slot used in data transfer.

2. A circuit arrangement for implementing a PLL in a time-division cellular network terminal in which power supply to at least some of the circuit elements of the terminal is arranged to be switched off for the duration of time slots not used in data transfer, comprising:

means for receiving an external signal and processing it into a reference signal,

means for indicating a signal representing a phase difference between said processed reference signal and a comparable signal generated in the circuit arrangement,

means for producing, using said indicated signal, a voltage change proportional to the phase difference,

a voltage controlled oscillator (VCG), for producing, on the basis of said voltage change proportional to the phase difference, an output signal having a varying frequency, and

means for switching off power supply of the VCO in the PLL for the duration of time slots not used in data transfer,

in which circuit arrangement a power supply voltage is arranged to be connected to the means for producing a voltage change proportional to the phase difference also during time slots not used in data transfer in order to reduce the restart time and switching noise in the PLL, wherein the means for producing an output signal having a varying frequency comprise a VCO which is arranged to be controlled using a control voltage obtained from an output of a low-pass filter, and

wherein the initial value of the VCO control voltage obtained from an output of a low-pass filter is arranged to be set, prior to the beginning of the next time slot used in data transfer, to a voltage value which is 100 to 200 mV above the VCO control voltage to be used in the next time slot used in data transfer.

3. A method for reducing the restart time and switching noise in a PLL circuit of a terminal used in a time-division cellular network, where:

at least a power supply of a VCO of the PLL is switched off for the duration of time slots not used in data transfer;

a power supply of a means controlling the frequency of an output signal of the VCO is not switched off for the duration of time slots not used for data transfer;

the power supply of the PLL and the VCO is switched on as a time slot assigned to the terminal for data transfer starts, and;

for the duration of a time slot assigned to data transfer the VCO operates at a frequency determined by a voltage value set at its control input

wherein as a time slot assigned to data transfer comes to an end, power supply to a reference divider, prescaler, programmable divider, and a phase comparator in the PLL is switched off as well.

4. A method for reducing the restart time and switching noise in a PLL circuit of a terminal used in a time-division cellular network, where:

at least a power supply of a VCO of the PLL is switched off for the duration of time slots not used in data transfer;

a power supply of a means controlling the frequency of an output signal of the VCO is not switched off for the duration of time slots not used for data transfer;

the power supply of the PLL and the VCO is switched on as a time slot assigned to the terminal for data transfer starts, and;

for the duration of a time slot assigned to data transfer the VCO operates at a frequency determined by a voltage value set at its control input, wherein as a time slot assigned to data transfer comes to an end, a target value is determined for the VCO control voltage to be used in the next time slot used in data transfer and

wherein the control voltage determining the frequency of the VCO output signal is set to a value which is 100 to 200 mV above that used in the next time slot used in data transfer.

5. A phase locked loop, comprising:

a phase comparator configured to compare an input signal to a reference signal to generate an output indicative of a difference in phase between the input signal and the reference signal;

a charge pump responsive to the output of the phase comparator to generate an output signal;

a voltage controlled oscillator responsive to the output of the charge pump to generate an output signal having a frequency related to the output signal of the charge pump, and

control circuitry configured to switch off a power supply voltage of said phase comparator and voltage controlled oscillator during a period of non-use, where a power supply voltage of said charge pump is not switched off during the period of non-use and where a bias current of said charge pump is switched off during the period of non-use to cause said output of said charge pump to assume a high impedance state during the period of non-use and to reduce power consumption of said charge pump.

6. The phase locked loop of claim 5, where said output of said charge pump is coupled to said voltage controlled oscillator via a filter, and where during the period of non-use an output voltage of said filter remains substantially constant.

7. The phase locked loop of claim 5, where the reference signal is derived from an output of said phase locked loop.

8. The phased locked loop as in claim 5, embodied in an integrated circuit.

9. The phased locked loop as in claim 5, embodied in a wireless terminal, where the period of non-use corresponds to a time when the wireless terminal is at least one of not receiving or transmitting.

10. The phased locked loop as in claim 5, embodied in a wireless terminal configured for use in a time divisional wireless network, where the period of non-use comprises at least one time slot when the wireless terminal is not receiving from the wireless network.

11. The phased locked loop as in claim 5, embodied in a wireless terminal configured for use in a time divisional wireless network, where the period of non-use comprises at least one time slot when the wireless terminal is not transmitting to the wireless network.

12. A phase locked loop (PLL) circuit, comprising:

a signal generator responsive to an external signal to output a reference signal;

a difference determining circuit configured to output a signal representing a phase difference between the reference signal and another signal;

a voltage circuit that outputs, in response to the output of said difference determining circuit, a voltage that has a value related to the phase difference,

a voltage controlled oscillator (VCO) configured to respond to a control voltage obtained from the voltage to output a signal having a frequency that is a function of the control voltage; and

switching circuitry configured to switch off a power supply voltage of the VCO for a duration of time slots not used for data transfer in a time-division cellular network,

where the power supply voltage is not switched off to the voltage circuit during those time slots not used in data transfer to reduce a restart time and to reduce switching noise of the PLL circuit.

13. The PLL circuit of claim 12, where said voltage circuit comprises a low-pass filter.

14. The PLL circuit of claim 13, where a bandwidth of the low-pass filter is less than about 10% of the frequency of the reference signal.

15. The PLL circuit of claim 13, where said voltage circuit further comprises a charge pump having an output coupled to the low-pass filter.

16. The PLL circuit of claim 15, where the output of the charge pump is configured to enter a high-impedance state to prevent a discharge of the low pass filter during a time slot not used in data transfer.

17. The PLL circuit of claim 12, where said control voltage is obtained from an output of a low pass filter.

18. The PLL circuit of claim 12, where the control voltage is set, at the end of a time slot used for data transfer, to a voltage value that is substantially equal to an initial value of the control voltage to be used in a next time slot used for data transfer.

19. The PLL circuit of claim 12, where the control voltage is set, prior to a beginning of a next time slot used for data transfer, to a voltage value that is substantially equal to an initial value of the control voltage to be used in the next time slot used for data transfer.

20. The PLL circuit of claim 12, where the control voltage is set, at a time prior to a beginning of a next time slot used for data transfer, to a voltage value that is greater than an estimated initial value of the control voltage to be used in the next time slot used for data transfer.

21. The PLL circuit of claim 12, where the control voltage is set, at a time prior to a beginning of a next time slot used for data transfer, to a voltage value that is about 100 mV to about 200 mV greater than an estimated initial value of the control voltage to be used in the next time slot used for data transfer.

22. The PLL circuit of claim 12, where the control voltage is set, at a time prior to a beginning of a next time slot used for data transfer, to a voltage value that is predetermined to cause said VCO to generate a frequency in the next time slot used for data transfer that is substantially equal to a frequency used in a last time slot used for data transfer.

23. The PLL circuit of claim 12, where the control voltage is set, at a time prior to a beginning of a next time slot used for data transfer, to a voltage value that is predetermined to cause said VCO to generate a frequency in the next time slot used for data transfer that is different than a frequency used in a last time slot used for data transfer.

24. The PLL circuit of claim 12, embodied at least partially in an integrated circuit.

25. The PLL circuit of claim 12, embodied in a terminal configured for use in the time-division cellular system.