Microcomputer logic development system

• US 7,283,946 B2
• Filed: 07/30/2003
• Issued: 10/16/2007
• Est. Priority Date: 11/30/2001
• Status: Expired due to Fees

• Current Assignee: Fujitsu Ten Limited (DENSO Corporation)
• Original Assignee: Fujitsu Ten Limited (DENSO Corporation)
• Inventors: Kashihara, Toshihiro, Imada, Shougo, Hiquchi, Takashi
• Primary Examiner(s): Rodriguez; Paul
• Assistant Examiner(s): Craig; Dwin McTaggart
• Application Number:
  US10/631,620
• Publication Number:
  US 20040031003A1
• Time in Patent Office: 1,539 Days
• Field of Search: 703/21, 703/24, 716/17, 701/29, 701/33
• US Class Current: 703/21
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Provided is a system for developing the preceding logic to be implemented in a built-in microcomputer that is used while being incorporated in an electronic control unit. The system has a CPU whose capability is good enough to implement the preceding logic. The system comprises: a motherboard having a first CPU, a first memory, and a first interface via which the motherboard communicates with the outside, interconnected over a first internal bus; a core board having a second CPU, a second memory, quasi microcomputer peripheral devices, which simulate by software the peripheral devices of a microcomputer, and a second interface via which the core board communicates with the outside, interconnected over a second internal bus; and a PCI bus that links the motherboard and core board. The development system is substituted for the built-in microcomputer in order to implement the preceding logic.

Claims

1. A system for developing logic to be implemented in a built-in microcomputer that is used while being incorporated in an electric control unit, comprising:

a center block including at least a first central processing unit associated with the logic, a first memory in which data including a program in which the logic is implemented is stored, a first interface via which said center block communicates with the outside, and a first internal bus over which said first central processing unit, said first memory, and said first interface are interconnected;

a peripheral block including one or more resources that simulate, by software, peripheral devices of the microcomputer, a second interface via which said peripheral block communicates with the outside, and a second internal bus over which said resources and said second interface are interconnected; and

an interface bus over which said center block and peripheral block are interconnected,

wherein, said center block, said peripheral block, and said interface bus are substituted for said built-in microcomputer in order to implement the logic,

wherein, a control application composed of a temporal interrupt handling application for temporal interrupt handling at regular intervals and a non-temporal interrupt handling application for non-temporal interrupt handling responsive to a predetermined event that is irrespective of time, is stored in said first memory,

wherein, said first central processing unit has a virtual interrupt controller facility that performs at least the temporal interrupt handling and the non-temporal interrupt handling,

wherein, communication software that transmits or receives at least data and interrupt event information over said interface bus is installed in said first interface,

wherein, a second central processing unit communicates with said first interface using a second memory and said second interface so as to transfer an interrupt event and data over said interface bus,

wherein, said resources include input facilities and output facilities,

wherein, said second memory includes a common memory connected on said interface bus, and

wherein, said resources transmit or receive data to or from said temporal interrupt handling application and said non-temporal interrupt handling application, which are stored in said first memory, via said common memory and said interface bus, and

wherein, a timing for activating resources is not fixed based on a predetermined sampling cycle but is determined arbitrarily, and a next timing for activating said resources is set a termination of said non-temporal interrupt handling application.

2. A microcomputer logic development system according to claim 1, wherein:

if the time elapsed since the timing for activating said resources to the termination of said non-temporal interrupt handling application installed in said center block exceeds a predetermined verification time, said resources are forcibly activated.

3. A microcomputer logic development system according to claim 1, wherein:

an interrupt event occurring in said resources is transmitted to said center block over said interface bus in order to run said non-temporal interrupt handling application; and

the next timing for activating said resources is set to the termination of said non-temporal interrupt handling application.

4. A microcomputer logic development system according to claim 1, wherein said non-temporal interrupt handling application determines the priorities of interrupt events that may occur in said resources, and handles the interrupt events, which are transmitted to said center block over said interface bus, according to the priorities.

5. A microcomputer logic development system according to claim 1 wherein, when no interrupt event occurs in said resources, transmission of information to said center block over said interface bus is omitted.

6. A microcomputer logic development system according to claim 1 wherein, when timer value acquisition is requested during said non-temporal interrupt handling, a timer value acquired over said interface bus is corrected with a timer value provided by a first timer included in said center block.

7. A microcomputer logic development system according to claim 1, wherein:

said common memory includes a communication synchronization counter; and

transmission and reception of data between said quasi microcomputer peripheral devices and said non-temporal interrupt handling application are synchronized based on said communication synchronization counter.