Methods and structures of providing modular integrated circuits

• US 7,284,226 B1
• Filed: 10/01/2004
• Issued: 10/16/2007
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kondapalli, Venu M.
• Primary Examiner(s): Dinh; Paul
• Application Number:
  US10/956,544
• Time in Patent Office: 1,110 Days
• Field of Search: 716 16- 17, 326/41, 326/101
• US Class Current: 326/41
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures

Abstract

Modular wafers and integrated circuits (ICs), and methods of manufacturing modular ICs. A modular wafer can be optionally divided in various ways to avoid defects while producing a variety of modular ICs. A modular wafer includes an array of element dice separated by a scribe area. The scribe area includes interconnect lines that extend across the scribe area between each adjacent pair of the element dice. Unused interconnect lines can be pulled to a known value using weak pullups or pulldowns. Modular ICs can be manufactured with interconnect lines between each pair of adjacent element dice, in which case a single mask set can be used to manufacture a family of programmable logic devices (PLDs).

Claims

1. A modular integrated circuit (IC) wafer, comprising:

an array comprising rows and columns of substantially similar element dice each comprising a programmable IC;

a scribe area separating each row and each column of the element dice one from another, wherein the scribe area comprises interconnect lines extending across the scribe area between each adjacent pair of the element dice; and

for each of the interconnect lines extending across the scribe area, a transistor situated at each end of the interconnect line and on each side of the scribe area, each of the transistors being coupled between an associated one of the interconnect lines and power high or ground, each of the transistors having a gate terminal connected to a programmable memory cell of the programmable IC.

2. The modular IC wafer of claim 1, wherein the element dice comprise programmable logic devices (PLDs).

3. The modular IC wafer of claim 2, wherein the PLDs comprise field programmable gate arrays (FPGAs).

4. The modular IC wafer of claim 2, wherein each PLD comprises a plurality of logic blocks, each of the logic blocks comprises a programmable interconnect element, and the interconnect lines extending across the scribe area couple a first programmable interconnect element in a first of the element dice to a second programmable interconnect element in a second of the element dice.

5. The modular IC wafer of claim 1, wherein each of the transistors comprises a pullup coupled between the associated interconnect line and power high.

6. The modular IC wafer of claim 1, wherein the array comprises exactly N rows and M columns of the element dice, N and M being positive integers, and wherein M is has a value selected from a group consisting of:

one and two.

7. The modular IC wafer of claim 6, wherein N is has a value selected from a group consisting of:

one, two, three, and four.

8. A modular integrated circuit (IC), comprising:

an array comprising rows and columns of substantially similar element dice each comprising a programmable IC, the array being manufactured as an integral physical unit optionally separable into the element dice;

a scribe area separating each row and each column of the element dice one from another, wherein the scribe area comprises interconnect lines extending across the scribe area between each adjacent pair of the element dice; and

for each of the interconnect lines extending across the scribe area, a transistor situated at each end of the interconnect line and on each side of the scribe area, each of the transistors being coupled between an associated one of the interconnect lines and power high or ground, each of the transistors having a gate terminal connected to a programmable memory cell of the programmable IC.

9. The modular IC of claim 8, wherein the element dice comprise programmable logic devices (PLDs).

10. The modular IC of claim 9, wherein the PLDs comprise field programmable gate arrays (FPGAs).

11. The modular IC of claim 9, wherein each PLD comprises a plurality of logic blocks, each of the logic blocks comprises a programmable interconnect element, and the interconnect lines extending across the scribe area couple together the programmable interconnect elements in two of the element dice.

12. The modular IC of claim 8, wherein each of the transistors comprises a pullup coupled between the associated interconnect line and power high.

13. The modular IC of claim 8, wherein the array comprises exactly N rows and M columns of the element dice, N and M being positive integers, and wherein M is has a value selected from a group consisting of:

one and two.

14. The modular IC of claim 13, wherein N is has a value selected from a group consisting of:

one, two, three, and four.