Stackable ceramic FBGA for high thermal applications

• US 7,285,442 B2
• Filed: 02/22/2005
• Issued: 10/23/2007
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corisis, David J., Kinsman, Larry D., Moden, Walter L., Mess, Leonard E.
• Primary Examiner(s): Kebede; Brook
• Assistant Examiner(s): Nguyen; Khiem D
• Application Number:
  US11/063,403
• Publication Number:
  US 20050146010A1
• Time in Patent Office: 973 Days
• Field of Search: 438/74, 438/107, 438/109, 438/112, 438/123, 438/613, 438/FOR.426, 257/686, 257/E25.006, 257/E25.013, 257/E25.017, 257/E25.027, 257/E23.085, 257/E21.614
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Claims

1. A method for forming an assembly comprising:

obtaining a first carrier having a plurality of sides and a cavity, a frustoconical surface on a portion of each side of the plurality of sides for nesting with a second assembly, a lip on a portion of a bottom surface of each side of the plurality of sides for nesting with a third assembly, and a plurality of circuits located in a portion of the cavity;

placing a semiconductor device having a plurality of bond pads located within the cavity of the first carrier;

forming a first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device;

filling a portion of the cavity in the first carrier using an encapsulant material; and

placing a second connector material located in the first carrier.

2. The method of claim 1, further comprising:

providing a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof; and

forming at least one second connector connected to the second connector material in the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

3. The method of claim 1, wherein the first carrier includes at least one fin on a portion thereof.

4. The method of claim 1, further comprising:

providing a second carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and a plurality of circuits located in a portion of the cavity thereon connected to the at least one aperture therethrough;

placing a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located within the cavity of the second carrier;

filling the portion of the cavity in the second carrier using an encapsulant material; and

placing connector material located in a second aperture in the second carrier connected to the second connector material in the first carrier.

5. An assembly method comprising:

forming a first carrier having a plurality of sides, an upper surface, a lower surface, a cavity, a frustoconical surface on a portion of each side of the plurality of sides for nesting with a second assembly, a lip on a portion of a bottom surface of each side of the plurality of sides for nesting with a third assembly, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

locating a semiconductor device having a plurality of bond pads located within the cavity of the first carrier; and

forming a first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device.

6. The method of claim 5, further comprising:

filling a portion of the cavity in the first carrier using an encapsulant material.

7. The method of claim 5, further comprising:

providing a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof; and

attaching the first carrier to the substrate by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

8. The method of claim 5, wherein the first carrier includes at least one fin on a portion thereof.

9. The method of claim 5, further comprising:

providing a second carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier, the second carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier; and

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located within the cavity of the second carrier.

10. The method of claim 9, further comprising:

stacking the second carrier on the first carrier by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the second carrier.

11. The method of claim 10, further comprising:

filling the portion of the cavity in the second carrier using an encapsulant material.

12. An assembly method comprising:

forming a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof and a plurality of circuits on the lower surface thereof;

forming a first carrier having a plurality of sides, an upper surface, a lower surface, a cavity, a frustoconical surface on a portion of each side for nesting with a side of a second carrier, a lip on a portion of a bottom surface of each side for nesting with a surface of a third carrier, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

locating a semiconductor device having a plurality of bond pads located within the cavity of the first carrier;

forming a first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device; and

attaching the first carrier to the upper surface of the substrate by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

13. The method of claim 12, further comprising:

filling a portion of the cavity in the first carrier using an encapsulant material.

14. The method of claim 12, further comprising:

providing a second carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located within the cavity of the second carrier; and

attaching the second carrier to the substrate by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the lower surface of the substrate.

15. The method of claim 12, further comprising:

providing a third carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier, the third carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a third semiconductor device having an active surface having a plurality of bond pads thereon, the third semiconductor device located within the cavity of the third carrier; and

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the third carrier and at least one bond pad of the plurality of bond pads on the active surface of the third semiconductor device located within the cavity of the third carrier.

16. The method of claim 15, further comprising:

providing a fourth carrier oriented with respect to the second carrier and positioned in the same direction as the second carrier, the fourth carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a fourth semiconductor device having an active surface having a plurality of bond pads thereon, the fourth semiconductor device located within the cavity of the fourth carrier; and

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of a second carrier and at least one bond pad of the plurality of bond pads on the active surface of the fourth semiconductor device located within the cavity of the fourth carrier.

17. The method of claim 12, wherein the first carrier includes at least one fin on a portion thereof.

18. The method of claim 15, further comprising:

stacking the third carrier on the first carrier by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

19. The method of claim 16, further comprising:

stacking the fourth carrier on the second carrier by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the second carrier and at least one circuit of the plurality of circuits on the lower surface of the substrate.

20. A method for forming an assembly comprising:

forming a substrate having an upper surface, a lower surface, a plurality of circuits on the upper surface thereof, and a plurality of circuits on the lower surface thereof;

forming a first carrier having a plurality of sides, a cavity, a frustoconical surface on a portion of each side for nesting with a second carrier, a lip on a portion of a bottom surface of each side for nesting with a bottom surface of a third carrier, and a plurality of circuits located in a portion of the cavity;

placing a semiconductor device having a plurality of bond pads located within the cavity of the first carrier;

forming a first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device;

placing a second connector material located in the first carrier;

forming at least one second connector connected to the second connector material in the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

21. The method of claim 20, further comprising:

providing a second carrier having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and a plurality of circuits located in a portion of the cavity thereon connected to the at least one aperture therethrough;

placing a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located within the cavity of the second carrier;

placing connector material located in a second aperture in the second carrier connected to a connector material in the at least one aperture in the second carrier; and

attaching the second carrier to the lower surface of the substrate by forming at least one connector connected to at least one contact pad of a plurality of contact pads on the lower surface of the second carrier and at least one circuit of the plurality of circuits on the lower surface of the substrate.

22. The method of claim 21, further comprising:

providing a third carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and a plurality of circuits located in a portion of the cavity thereon connected to the at least one aperture therethrough;

placing a third semiconductor device having an active surface having a plurality of bond pads thereon, the third semiconductor device located within the cavity of the third carrier;

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the third carrier and at least one bond pad of the plurality of bond pads on the active surface of the third semiconductor device located within the cavity of the third carrier;

filling the portion of the cavity in the third carrier using an encapsulant material; and

placing connector material located in a second aperture in the third carrier connected to a connector material in the at least one aperture in the first carrier.

23. The method of claim 22, further comprising:

providing a fourth carrier oriented with respect to the third carrier and positioned in the same direction as the third carrier, the fourth carrier having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and a plurality of circuits located in a portion of the cavity thereon connected to the at least one aperture therethrough;

placing a fourth semiconductor device having an active surface having a plurality of bond pads thereon, the fourth semiconductor device located within the cavity of the fourth carrier;

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the fourth carrier and at least one bond pad of the plurality of bond pads on the active surface of the fourth semiconductor device located within the cavity of the fourth carrier;

filling the portion of the cavity in the fourth carrier using an encapsulant material; and

placing connector material located in a second aperture in the fourth carrier connected to the connector material in the at least one aperture in the third carrier.

24. A method of stacking a plurality of semiconductor devices using carriers for forming an assembly comprising:

forming a first carrier having a plurality of sides, a cavity, a frustoconical surface on a portion of each side for nesting with another side of a second carrier, a lip on a portion of a bottom surface of each side for nesting with a side of a third carrier, and a plurality of circuits located in a portion of the cavity;

placing a semiconductor device having a plurality of bond pads located within the cavity of the first carrier;

forming a first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device;

filling a portion of the cavity in the first carrier using an encapsulant material; and

placing a second connector material located in the first carrier.

25. The method of claim 24, further comprising:

providing a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof; and

forming at least one second connector connected to a connector material in a at least one aperture in the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

26. The method of claim 24, wherein the first carrier includes at least one fin on a portion thereof.

27. The method of claim 24, further comprising:

providing a second carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and a plurality of circuits located in a portion of the cavity thereon connected to the at least one aperture therethrough;

placing a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located within the cavity of the second carrier;

filling the portion of the cavity in the second carrier using an encapsulant material; and

placing connector material located in a second aperture in the second carrier connected to a connector material in the at least one aperture in the first carrier.

28. A method of stacking a plurality of semiconductor devices using carriers for forming an assembly comprising:

forming a first carrier having a plurality of sides, an upper surface, a lower surface, a cavity, a frustoconical surface on a portion of each side for nesting with another side of a second carrier, a lip on a portion of a bottom surface for nesting with another surface of a third carrier, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

locating a semiconductor device having a plurality of bond pads located within the cavity of the first carrier; and

forming a first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device.

29. The method of claim 28, further comprising:

filling a portion of the cavity in the first carrier using an encapsulant material.

30. The method of claim 28, further comprising:

providing a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof; and

attaching the first carrier to the substrate by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

31. The method of claim 28, wherein the first carrier includes at least one fin on a portion thereof.

32. The method of claim 28, further comprising:

providing a second carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier, the second carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier; and

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located in the cavity of the second carrier.

33. The method of claim 32, further comprising:

stacking the second carrier on the first carrier by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

34. The method of claim 33, further comprising:

filling the portion of the cavity in the second carrier using an encapsulant material.

35. A method for stacking a plurality of semiconductor devices using carriers for forming an assembly comprising:

obtaining a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof and a plurality of circuits on the lower surface thereof;

obtaining a first carrier having a plurality of sides, an upper surface, a lower surface, a cavity, a frustoconical surface on a portion of each side for nesting with a portion of a side of a second carrier, a lip on a portion of a bottom surface of each side for nesting with a portion of a surface of a third carrier, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

locating a semiconductor device having a plurality of bond pads located within the cavity of the first carrier;

forming a first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads of the semiconductor device; and

attaching the first carrier to the upper surface of the substrate by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

36. The method of claim 35, further comprising:

filling a portion of the cavity in the first carrier using an encapsulant material.

37. The method of claim 35, further comprising:

providing a second carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device located in the cavity of the second carrier; and

attaching the second carrier to the substrate by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the second carrier and at least one circuit of the plurality of circuits on the lower surface of the substrate.

38. The method of claim 37, further comprising:

providing a third carrier oriented with respect to the first carrier and positioned in the same direction as the first carrier, the third carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a third semiconductor device having an active surface having a plurality of bond pads thereon, the third semiconductor device located within the cavity of the third carrier; and

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the third carrier and at least one bond pad of the plurality of bond pads on the active surface of the third semiconductor device located in the cavity of the third carrier.

39. The method of claim 38, further comprising:

providing a fourth carrier oriented with respect to the second carrier and positioned in the same direction as the second carrier, the fourth carrier having an upper surface, a lower surface, a cavity, a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, a lip on a portion of a bottom surface thereof, a plurality of circuits located in a portion of the cavity, at least one circuit of the plurality of circuits located in a portion of the cavity extending to at least one contact pad of a plurality of contact pads on the upper surface, a plurality of contact pads on the lower surface, and a plurality of internal circuits extending between at least one of the plurality of contact pads on the upper surface and at least one of the plurality of contact pads on the lower surface;

placing a fourth semiconductor device having an active surface having a plurality of bond pads thereon, the fourth semiconductor device located within the cavity of the fourth carrier; and

forming another first connector between at least one circuit of the plurality of circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the fourth semiconductor device located within the cavity of the fourth carrier.

40. The method of claim 38, further comprising:

stacking the third carrier on the first carrier by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate.

41. The method of claim 39, further comprising:

stacking the fourth carrier on the second carrier by forming at least one second connector connected to at least one contact pad of the plurality of contact pads on the lower surface of the second carrier and at least one circuit of the plurality of circuits on the lower surface of the substrate.