Nonvolatile storage array with continuous control gate employing hot carrier injection programming
First Claim
1. A method of programming a storage cell in an array of storage cells, comprising:
- providing the array of storage cells, including a storage cell, the array comprising;
a semiconductor layer;
a first trench and a second trench spaced-apart from one another, wherein;
each of the first trench and the second trench extends from a surface of the semiconductor layer;
a portion of the semiconductor layer lies between the first and second trenches; and
the portion of the semiconductor layer has a first wall immediately adjacent to the first trench and a second wall immediately adjacent to the second trench;
a first control gate extending into the first trench;
a first source/drain region underlying the first trench;
a second source/drain region that;
lies within the portion of the semiconductor layer and adjacent to the surface of the semiconductor layer, wherein the second source/drain region is spaced apart from the first wall, the second wall, or both the first and second walls;
orunderlies the second trench;
a first set of discontinuous storage elements lying between the first control gate and the first wall of the portion of the semiconductor layer; and
a second set of discontinuous storage elements lying between;
the first control gate; and
a part of the semiconductor layer at the surface of the portion of the semiconductor layer, wherein the part of the semiconductor layer lies outside the second source/drain region; and
biasing the first source/drain region to a drain programming voltage (VPD);
biasing the second source/drain region to 0 V; and
biasing the first control gate to a gate programming voltage (VPG) to program a first bit of the storage cell by injecting charge into the first set of the discontinuous storage elements adjacent to the first wall of the portion of the semiconductor layer.
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Accused Products
Abstract
An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
56 Citations
9 Claims
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1. A method of programming a storage cell in an array of storage cells, comprising:
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providing the array of storage cells, including a storage cell, the array comprising; a semiconductor layer; a first trench and a second trench spaced-apart from one another, wherein; each of the first trench and the second trench extends from a surface of the semiconductor layer; a portion of the semiconductor layer lies between the first and second trenches; and the portion of the semiconductor layer has a first wall immediately adjacent to the first trench and a second wall immediately adjacent to the second trench; a first control gate extending into the first trench; a first source/drain region underlying the first trench; a second source/drain region that; lies within the portion of the semiconductor layer and adjacent to the surface of the semiconductor layer, wherein the second source/drain region is spaced apart from the first wall, the second wall, or both the first and second walls;
orunderlies the second trench; a first set of discontinuous storage elements lying between the first control gate and the first wall of the portion of the semiconductor layer; and a second set of discontinuous storage elements lying between; the first control gate; and a part of the semiconductor layer at the surface of the portion of the semiconductor layer, wherein the part of the semiconductor layer lies outside the second source/drain region; and biasing the first source/drain region to a drain programming voltage (VPD); biasing the second source/drain region to 0 V; and biasing the first control gate to a gate programming voltage (VPG) to program a first bit of the storage cell by injecting charge into the first set of the discontinuous storage elements adjacent to the first wall of the portion of the semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification