High mobility CMOS circuits

• US 7,285,826 B2
• Filed: 10/06/2005
• Issued: 10/23/2007
• Est. Priority Date: 11/06/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Zhu, Huilong, Gluschenkov, Oleg G.
• Primary Examiner(s): Crane; Sara
• Assistant Examiner(s): Gebremariam; Samuel A.
• Application Number:
  US11/244,291
• Publication Number:
  US 20060027868A1
• Time in Patent Office: 747 Days
• Field of Search: 257/351, 257/368, 257/369, 257/635, 257/637, 257/639, 438/153, 438/157, 438/197
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

Claims

1. A semiconductor structure formed on a sustrate comprising:

a plurality of field effect transitors having a first portion of field effect transitors (FETS) and a second portion of field effect transitors;

a first stress layer having a first thickness and being configured to impart a first determined stress to the first portion of the plurality of field effect transitors; and

a second stress layer having a second thickness and being configured to impart a second determined stress to the second portion of the plurality of field effect transistors,

wherein the first thickness is different than the second thickness and the first portion of field effect transitors has a different spacing or density than the second portion of field effect transitors.

2. The semiconductor structure according to claim 1, wherein:

the first portion of the plurality of field effect transitors have spacing between adjacent field effect transitors that fall within a first defined spacing range; and

the second portion of the plurality of field effect transitors have spacings between adjacent field effect transitors that fall within a second defined spacing range.

3. The semiconductor structure according to claim 1, wherein:

the first defined spacing range is less than the second defined spacing range; and

the first thickness is less than the second thickness.

4. The semiconductor structure according to claim 3, wherein the first thickness does not pose a substantial risk to void formation in the first stress layer.

5. The semiconductor structure according to claim 2, wherein:

the first determined stress enhances performance of the first portion of the plurality of field effect transitors, without materially degrading performance of any of the plurality of FETs that are not in the first portion; and

the second determined stress enhances performance of the second portion of the plurality of field effect transitors, without materially degrading performance of any of the plurality of FETs that are not in the second portion.

6. The semiconductor structure according to claim 5, wherein:

the first portion of the plurality of field effect transistors is comprised of n-channel field effect transistors;

the first determined stress is a tensile stress;

the second portion of the plurality of field effect transistors is comprised of p-channel field effect transistors; and

the second determined stress is a compressive stress.

7. The semiconductor structure according to claim 6, wherein:

the first stress layer is formed by a chemical vapor deposition process using a temperature of about 480°

C., a pressure of about 6.25 Torr, a spacing between the semiconductor structure and CVD electrode of about 490 mils, a flow of about 300 scm of 2% dilate SiH₄ gas, about 15 sccm NH₃ gas and about 1060 sccm N₂ gas using RF power of about 340 watts.

8. The semiconductor structure according to claim 6, wherein:

the second stress layer is formed by a chemical vapor deposition process using a temperature of about 480°

, a pressure of about 5.75 Torr, a spacing between the semiconductor structure and CVD electrode of about 395 mils, a flow of about 3000 sccm of 2% dilute SiH₄ gas, about 15 sccm of NH₃ gas and 1060 sccm of N₂ gas using RF power of 900 watts.

9. The semiconductor structure according to claim 5, wherein:

the first portion of the plurality of field effect transistors is comprised of n-channel field effect transistors;

the first determined stress is a tensile stress;

the first defined spacing range is less than the second defined spacing range; and

the second portion of the plurality of field effect transistors is comprised of n-channel field effect transistors;

the second determined stress is a tensile stress;

the first thickness is less than the second thickness; and

the first thickness does not pose a substantial risk of void formation in the first stress layer.

10. The semiconductor structure according to claim 5, wherein:

the first portion of the plurality of field effect transistors is comprised of p-channel field effect transistors;

the first determined stress is a compressive stress;

the first defined spacing range is less than the second defined spacing range; and

the second portion of the plurality of field effect transistors is comprised of p-channel field effect transistors;

the second determined stress is a compressive stress;

the first thickness is less than the second thickness; and

the first thickness does not pose a substantial risk of void formation in the first stress layer.

11. A semiconductor structure formed on a substrate comprising:

a first plurality of n-channel field effect transistors having spacings between adjacent n-channel field effect transistors that fall within a first defined spacing range;

a second plurality of n-channel field effect transistors having spacings between adjacent n-channel field effect transistors that fall within a second defined spacing range;

a first plurality of p-channel field effect transistors having spacings between adjacent p-channel field effect transistors that fall within a third defined spacing range;

a second plurality of p-channel field effect transistors having spacings between adjacent p-channel field effect transistors that fall within a fourth defined spacing range;

a first tensile layer having a first tensile layer thickness and being configured to impart a first determined tensile stress to the first plurality of n-channel field effect transistors;

a second tensile layer having a second tensile layer thickness and being configured to impart a second determined tensile stress to the second plurality of n-channel field effect transistors;

a first compressive layer having a first compressive layer thickness and being configured to impart a first determined compressive stress to the first plurality of p-channel field effect transistors; and

a second compressive layer having a second compressive layer thickness and being configured to impart a second determined compressive stress to the second plurality of p-channel field effect transistors.

12. The semiconductor structure according to claim 11, wherein each of the first tensile layer;

second tensile layer;

first compressive layer and second compressive layer is deposited on an SiO₂ liner.

13. The semiconductor structure according to claim 11, wherein:

the first defined spacing range is less than the second defined spacing range; and

the third defined spacing range is less than the fourth defined spacing range.

14. The semiconductor structure according to claim 13, wherein:

the first tensile layer thickness is less than the second tensile layer thickness; and

the first compressive layer thickness is less than the second compressive layer thickness.

15. The semiconductor structure according to claim 14, wherein:

the first tensile layer thickness does not pose a substantial risk of void formation in the first tensile layer; and

the first compressive layer thickness does not pose a substantial risk of void formation in the first compressive layer.

16. The semiconductor structure according to claim 15, wherein:

the first determined tensile stress enhances electron mobility in the first plurality of n-channel field effect transistors, without materially degrading performance of the first plurality of p-channel field effect transistors and the second plurality of p-channel field effect transistors; and

the first determined compressive stress enhances hole mobility in the first plurality of p-channel field effect transistors, without materially degrading performance of the first plurality of n-channel field effect transistors and the second plurality of n-channel field effect transistors.

17. The semiconductor structure according to claim 16, wherein:

the first tensile layer thickness is proportional to the first determined spacing range;

the second tensile layer thickness is proportional to the second determined spacing range;

the first compressive layer thickness is proportional to the third determined spacing range; and

the second compressive layer thickness is proportional to the fourth determined spacing range.

18. The semiconductor structure according to claim 16, wherein the first tensile layer, second tensile layer, first compressive layer and second compressive layer, are comprised of materials from the group consisting of silicon nitride and silicon oxynitride.

19. The semiconductor structure according to claim 16, wherein:

the first tensile layer and second tensile layer each exhibit a tensile stress of about 600 to 1500 MPa; and

the first compressive layer and second compressive layer each exhibit a compressive stress of about −

600 to −

1500 MPa.

20. A process of forming a semiconductor structure, comprising:

forming a plurality of field effect transistors on a semiconductor substrate, the plurality of field effect transistors including a first portion of field effect transistors and a second portion of field effect transistors;

depositing a first stress layer having a first thickness and being configured to impart a first determined stress to the first portion of the plurality of field effect transistors; and

depositing a second stress layer having a second thickness and being configured to impart a second determined stress to the second portion of the plurality of field effect transistors,

wherein the first thickness is different than the second thickness and the first portion of field effect transistors has a different spacing or density than the second portion of field effect transistors.

21. A process of forming a semiconductor structure according to claim 20, further comprising:

removing portions of the first stress layer from areas of the semiconductor that would not experience performance enhancement due to the first determined stress; and

removing portions of the second stress layer from areas of the semiconductor that would not experience performance enhancement due to the second determined stress.

22. A process of forming a semiconductor structure according to claim 21, wherein the first thickness is less than the second thickness.

23. A semiconductor circuit comprising a substrate;

a plurality of field effect transistors formed on the substrate, the plurality of field effect transistors including a first portion of field effect transistors and a second portion of field effect transistors;

a first stress layer having a first thickness and being configured to impart a first determined stress to the first portion of the plurality of field effect transistors;

a second stress layer having a second thickness and being configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

the first portion of the plurality of field effect transistors have spacings between adjacent field effect transistors that fall within a first defined spacing range; and

the second portion of the plurality of field effect transistors have spacings between adjacent field effect transitors that fall within a second defined spacing range,

wherein;

the first defined spacing range is less than the second defined spacing range; and

the first thickness is less than the second thickness.