Multiple internal seal right micro-electro-mechanical system vacuum package

• US 7,285,844 B2
• Filed: 06/10/2004
• Issued: 10/23/2007
• Est. Priority Date: 06/10/2003
• Status: Active Grant

• Current Assignee: California Institute of Technology, The Boeing Co.
• Original Assignee: California Institute of Technology, The Boeing Co.
• Inventors: Bae, Youngsam, Shcheglov, Kirill V., Challoner, A. Dorian, Hayworth, Ken J., Wiberg, Dean V., Yee, Karl Y., Peay, Chris S.
• Primary Examiner(s): Ahmed; Shamim
• Application Number:
  US10/865,344
• Publication Number:
  US 20050017329A1
• Time in Patent Office: 1,230 Days
• Field of Search: 257/659, 257/660, 438/455, 438/456, 216/2
• US Class Current: 257/659
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: G01C 19/5719 using planar vibrating masses driven in a translation vibration along an axis

Abstract

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum package that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Claims

1. A device package, comprising:

a capping plate including at least one periphery seal ring and at least one internal seal ring bonded to a base plate including at least one periphery seal ring and at least one internal seal ring;

wherein the periphery seal rings of the capping plate and base plate create a metal-to-metal seal surrounding the periphery of the package when the capping plate and the base plate are bonded together,

the internal seal rings of the capping plate electrically connect to a plurality of via holes extending through to an external surface of the capping plate,

the internal seal rings of the base plate provide an independent electrical path from a cavity in the capping plate outward towards a periphery of the base plate, and

the internal seal rings of the capping plate and the base plate create a metal-to-metal seal within the periphery of the package when the base plate and the capping plate are bonded together.

2. The device package of claim 1, wherein each seal ring serves the dual purposes of hermetic sealing and providing an electrical feed-through metal trace.

3. The device package of claim 1, wherein the device package is sealed by compression bonding of the seal rings of the capping plate and base plate.

4. The device package of claim 1, wherein the seal rings of the capping plate and the seal rings of the base plate provide a metal-to-metal seal between the base plate and the capping plate, when the base plate and the capping plate are bonded together.

5. The device package of claim 1, wherein the via holes through the capping plate provide electrical connection from outside the device package through the via-holes to inside the device package.

6. The device package of claim 1, wherein each via hole extends through the capping plate from a bottom surface to a top surface of the capping plate.

7. The device package of claim 1, wherein each via hole electrically connects to an electrical trace pattern on the top surface of the capping plate.

8. The device package of claim 1, wherein a plurality of the capping plates are fabricated on a capping plate wafer and a plurality of the base plates are fabricated on a base plate wafer.

9. The device package of claim 1, wherein the capping plate wafer is bonded to the base plate wafer.

10. The device package of claim 1, wherein bulk electrodes provide conductive paths between the seal rings on the base plate and the capping plate.

11. The device package of claim 1, wherein the bulk electrodes are fabricated from a resonator plate wafer bonded to the base plate wafer.

12. A device packaged using a method comprising the steps of:

(a) metal patterning of at least one seal ring on a base plate;

(b) etching of via holes in a capping plate;

(c) metal patterning of at least one seal ring on a bottom surface of the capping plate;

(d) aligning of the base plate and capping plate;

(e) bonding of the base plate and capping plate;

(f) electro-less plating of a thin metal layer on a top surface of the capping plate, including inside the via holes;

(g) electroplating of a thicker metal layer on top of the thin metal layer; and

(h) masking and etching of electrical trace patterns on the top surface of the capping plate.

13. The device of claim 12, wherein the device comprises a surface-processed micro-electro-mechanical system (MEMS) device etched directly from the base plate wafer.

14. A device packaged using a method comprising the steps of:

(a) metal patterning of at least one seal ring on a base plate;

(b) aligning of the base plate and a resonator plate;

(c) bonding of the base plate and resonator plate using heat and pressure in an evacuated chamber;

(d) etching of bulk electrodes on the resonator plate, wherein the doped silicon or a metalization of the resonator plate provides a conductive path for the electrodes;

(e) etching of at least one via hole in a capping plate;

(f) metal patterning of at least one seal ring on a bottom surface of the capping plate;

(g) aligning of the resonator plate and capping plate, and more specifically, the aligning of the bulk electrodes of the resonator plate with the seal rings of the capping plate;

(h) bonding of the of the resonator plate and capping plate using heat and pressure in an evacuated chamber;

(i) electro-less plating of a thin metal layer on a top surface of the capping plate including inside the via holes;

(j) electroplating of a thicker metal layer on the thin metal layer;

(k) masking and etching of an electrical trace pattern on the top surface of the capping plate.

15. The device of claim 14, wherein the device comprises a two-wafer bulksilicon-etched micro-electro-mechanical system (MEMS) device etched from the bonded base plate wafer and resonator wafer.