Delay-locked loop

• US 7,285,996 B2
• Filed: 09/30/2005
• Issued: 10/23/2007
• Est. Priority Date: 09/30/2005
• Status: Expired due to Fees

• Current Assignee: SLT Logic LLC
• Original Assignee: SLT Logic LLC
• Inventors: Fiedler, Alan
• Primary Examiner(s): Cox, Cassandra
• Application Number:
  US11/241,230
• Publication Number:
  US 20070075758A1
• Time in Patent Office: 753 Days
• Field of Search: None
• US Class Current: 327/158
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A delay locked loop (DLL) circuit that includes a delay line having a plurality of delay elements. Each delay element can be adapted to receive a clock input signal and generate a clock output signal, where the phase of each clock output signal is offset from the clock input signal. The delay line can be configured so that one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal. The feedback portion of the circuit can be configured to generate delay adjust signals based upon the phase offsets between pairs of clock signals. The delay adjust signals are fed back to the delay elements causing the reference input clock signal and the clock output signals to be phase-shifted apart equally about 360 degrees.

Claims

1. A delay locked loop (DLL) circuit comprising:

a delay line comprising serially connected first and second delay elements with said second delay element serially connected to a duty cycle monitor, wherein each delay element is adapted to receive at least a clock input signal and output at least a clock output signal with a phase offset from said clock input signal, the delay line configured so that at least one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal; and

a feedback circuit configured to generate delay adjust signals based upon said phase offsets between at least one pair of signals selected from a set containing said reference input clock signal and said clock output signals, said delay adjust signals being fed back to at least one of said plurality of delay elements to cause said reference input clock signal to said plurality of clock output signals to be progressively phase-shifted apart equally about 360 degrees.

2. A delay locked loop (DLL) circuit comprising:

a delay line including serially connected first and second delay elements with said second delay element serially connected to a duty cycle monitor, wherein each delay element is adapted to receive at least a clock input signal and output at least a clock output signal with a phase offset from said clock input signal, the delay line configured so that at least one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal;

wherein the first delay element is configured to take a reference clock input signal and output a first clock output signal delayed by a first time delay;

the second delay element configured to take the first clock output signal and output a second clock output signal delayed by a second time delay; and

the duty cycle monitor adapted to receive the second clock output signal and output a duty cycle corrected signal by correcting a duty of the second clock output signal, said duty cycle output corrected signal being fed back to each of said first clock output signal and said second clock output signal; and

a feedback circuit configured to generate delay adjust signals based upon said phase offsets between at least one pair of signals selected from a set containing said reference input clock signal and said clock output signals, said delay adjust signals being fed back to at least one of said plurality of delay elements to cause said reference input clock signal to said plurality of clock output signals to be progressively phase-shifted apart equally about 360 degrees wherein said feedback circuit is further configured to generate a reference current corresponding to the phase shift between the reference clock input signal and the second clock output signal, a first phase shift current corresponding to phase shift between the input reference clock and the first clock output signal, and a second phase shift current corresponding to the phase shift between the first and second output clock signal, the feedback circuit adapted to output a first and second delay adjust signals based upon differences between the phase shift currents and the reference current, said first delay adjust signal being fed back to said first delay element and said second delay adjust signal being fed back to said second delay element causing said reference clock input signal, said first clock output signal and said second clock output signal to be progressively phase-shifted apart equally about 360 degrees.

3. A delay locked loop (DLL) circuit comprising:

a delay line including a plurality of delay elements wherein each delay element is adapted to receive at least a clock input signal and output at least a clock output signal with a phase offset from said clock input signal, the delay line configured so that at least one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal; and

a feedback circuit configured to generate delay adjust signals based upon said phase offsets between at least one pair of signals selected from a set containing said reference input clock signal and said clock output signals, said delay adjust signals being fed back to at least one of said plurality of delay elements to cause said reference input clock signal and said plurality of clock output signals to be progressively phase-shifted apart equally about 360 degrees;

wherein the feedback circuit includes;

a first pair of cross-coupled transistors forming a first current mirror, said first pair of cross-coupled transistors having a first and a second current mirror transistor, and a first set of three series-connected reference transistors, each having a reference bias voltage input, said first set of series connected reference transistors being connected to the first current mirror transistor; and

a first pair of signals selected from the set containing said reference input clock signal and said clock output signals, said first pair of signals input to a pair of series connected transistors connected to said second current mirror transistor to generate a first reference current and a first delay signal;

a second pair of cross-coupled transistors forming a second current mirror, said second pair of cross-coupled transistors having a first and a second current mirror transistor, and a set of three series-connected reference transistors, each having a reference bias voltage input, said set of series connected reference transistors being connected to the first current mirror transistor; and

a second pair of signals selected from the set containing said reference input clock signal and said clock output signals, said second pair of signals input to a pair of series connected transistors connected to said second current minor transistor to generate a second reference current and a second delay signal;

a third pair of cross-coupled transistors forming a third current minor, said third pair of cross-coupled transistors having a first and a second current mirror transistor, and a set of three series-connected reference transistors, each having a reference bias voltage input, said set of series connected reference transistors being connected to the first current mirror transistor; and

a third pair of signals selected from the set containing said reference input clock signal and said clock output signals, said third pair of signals input to a pair of series connected transistors connected to said second current mirror transistor to generate a third reference current; and

a tail bias circuit summing the reference currents;

such that said feedback circuit stabilizes when said reference currents become substantially equal.

4. A delay locked loop (DLL) circuit comprising:

a delay line including serially connected first and second delay elements with said second delay element serially connected to a duty cycle monitor, wherein each delay element is adapted to receive at least a clock input signal and output at least a clock output signal with a phase offset from said clock input signal, the delay line configured so that at least one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal;

a feedback circuit configured to generate delay adjust signals based upon said phase offsets between at least one pair of signals selected from a set containing said reference input clock signal and said clock output signals, said delay adjust signals being fed back to at least one of said plurality of delay elements to cause said reference input clock signal to said plurality of clock output signals to be progressively phase-shifted apart equally about 360 degrees wherein the first delay element is configured to take a reference clock input signal and output a first clock output signal delayed by a first time delay;

the second delay element configured to take the first clock output signal and output a second clock output signal delayed by a second time delay; and

the duty cycle monitor adapted to receive the second clock output signal and output a duty cycle corrected signal by correcting a duty of the second clock output signal, said duty cycle output corrected signal being fed back to each of said first clock output signal and said second clock output signal, the feedback circuit further including a portion of a time-division multiplexer embedded within the feedback circuit wherein the time-division multiplexer is configured to receive the reference clock input signal, the first and second clock output signals and an incoming data stream, to sample the incoming data stream with the clock signals, and to generate a first and a second set of multiplexer output signals, wherein the output signals correspond to the first set of multiplexer output signals being the inverse of the second, and each multiplexer output signal having a corresponding pulse width, wherein the feedback circuit is adapted to receive the multiplexer output signals, measure the pulse width of each multiplexer output signal and to output a first and second delay adjust signal for feeding back to a first and a second delay element to cause the pulse widths to be substantially equal; and

wherein said feedback circuit is further configured to generate a reference current corresponding to the phase shift between the reference clock input signal and the second clock output signal, a first phase shift current corresponding to phase shift between the input reference clock and the first clock output signal, and a second phase shift current corresponding to the phase shift between the first and second output clock signal, the feedback circuit adapted to output a first and second delay adjust signals based upon differences between the phase shift currents and the reference current, said first delay adjust signal being fed back to said first delay element and said second delay adjust signal being fed back to said second delay element causing said reference clock input signal, said first clock output signal and said second clock output signal to be progressively phase-shifted apart equally about 360 degrees.

5. The delay-locked loop of claim 4 wherein the first set of multiplexer output signals comprises a first, second, and third multiplexer output, wherein each of a first set of multiplexer output signals comprises a combination of the incoming data stream, a clock output signal, and a clock output signal or reference clock input signal, and each of the multiplexer outputs has a corresponding pulse width such that a sum of the pulse widths of all outputs in the set substantially equals a period of the reference clock, and a second set of multiplexer output signals comprises a first, second, and third multiplexer output, wherein the first, second, and third multiplexer outputs of the second set of multiplexer output signals are substantially inversions of the multiplexer outputs of the first set of multiplexer output signals, respectively.

6. The delay-locked loop of claim 5 wherein the feedback circuit is further adapted to generate a pulse width reference current corresponding to the pulse width of the first multiplexer output of either the first or second set of multiplexer output signals, a first pulse width current corresponding to the pulse width of the second multiplexer output of either the first or second set of multiplexer output signals, and a second pulse width current corresponding to the pulse width of the third multiplexer output of either the first or second set of multiplexer output signals, the feedback circuit adapted to output a first and second delay adjust signals based upon differences between the pulse width currents and the pulse width reference current, said first delay adjust signal being fed back to said first delay element and said second delay adjust signal being fed back to said second delay element causing the pulse widths of all the multiplexer outputs to be substantially equal.

7. A delay locked-loop system comprising:

at least two delay-locked loops coupled together, generating multiple clock phase outputs equally spaced about 360 degrees, such that the spacing between generated clock phases is less than the delay through a single delay element in a delay-locked loop;

wherein a first delay-locked loop comprising a delay line generates a first set of clock phase outputs equally spaced about 360 degrees; and

a feedback loop including a feedback circuit which measures the set of clock phase outputs and provides an adjusted control output signal for each clock phase to the delay line such that the set of clock phase outputs are equally spaced about 360 degrees; and

a second delay-locked loop coupled to the first delay-locked loop such that the rising edges of its second set of clock phases lie substantially halfway between the rising edges of the first delay-locked loop'"'"'s first set of clock phases.

8. A method for producing a set of synchronized clock signals, the method comprising the steps of:

generating a plurality of phase-shifted clock outputs from a delay line including at least two adjustable delay elements and a duty cycle monitor communicatively coupled to each other, whereby each adjustable delay element in conjunction with the duty cycle monitor accepts an input clock signal concurrently with a delay adjust signal and generates the phase-shifted clock output; and

adjusting the phases of the phase-shifted clock outputs by measuring each phase-shift with a feedback circuit and generating a delay-adjust signal for each clock phase to the delay line such that the plurality of phase-shifted clock outputs are equally spaced substantially about 360 degrees.

9. A delay locked loop (DLL) circuit comprising:

a means for generating a plurality of phase-shifted clock outputs from a delay line that includes at least two adjustable delay elements and a duty cycle monitor communicatively coupled to each other, whereby each adjustable delay element in conjunction with the duty cycle monitor includes a means for accepting an input clock signal concurrently with a delay adjust signal and a means for generating the phase-shifted clock output; and

a means for adjusting the phases of the phase-shifted clock outputs by measuring each phase-shift with a feedback circuit and generating a delay-adjust signal for each clock phase to the delay line such that the plurality of phase-shifted clock outputs are equally spaced substantially about 360 degrees.