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Bit line selection transistor layout structure

  • US 7,286,396 B2
  • Filed: 10/12/2005
  • Issued: 10/23/2007
  • Est. Priority Date: 10/12/2005
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • a bit line;

    a first Bit Line Transistor (BLT) coupled to the bit line, the first BLT comprising a channel; and

    a second BLT coupled to the bit line, the second BLT comprising a channel, the dimensions of which are different from the dimensions of the first BLT channel, wherein the channel dimensions for the first and second BLTs comprise a channel width, and wherein the channel width for the first BLT is wider than the channel width for the second BLT.

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