Bit line selection transistor layout structure

• US 7,286,396 B2
• Filed: 10/12/2005
• Issued: 10/23/2007
• Est. Priority Date: 10/12/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Yang, Ling Kuey, Wu, Po Hsuan, Huang, Lan Ting, Liu, Chen Chin
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/248,506
• Publication Number:
  US 20070081383A1
• Time in Patent Office: 741 Days
• Field of Search: 365/72
• US Class Current: 365/177
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit line loading uniformity and provide greater uniformity in bit line bias. Additionally, the greater uniformity in bit line bias can improve reliability.

Claims

1. A memory device comprising:

a bit line;

a first Bit Line Transistor (BLT) coupled to the bit line, the first BLT comprising a channel; and

a second BLT coupled to the bit line, the second BLT comprising a channel, the dimensions of which are different from the dimensions of the first BLT channel, wherein the channel dimensions for the first and second BLTs comprise a channel width, and wherein the channel width for the first BLT is wider than the channel width for the second BLT.

2. The memory device of claim 1, wherein the channel dimensions for the first and second BLTs comprise a channel length, and wherein the channel length for the first BLT is shorter than the channel length for the second BLT.

3. The memory device of claim 1, further comprising a Y-decoder, coupled to the first and second BLTs through a bit line and proximate to the second BLT.

4. The memory device of claim 1, wherein the first and second BLTs are in different sectors.

5. The memory device of claim 1, wherein the first and second BLTs are in the same sector.

6. A method of designing a memory device comprising:

determining desired bit line loading;

calculating a bit line transistor dimension that will achieve the desired bit line loading; and

modifying the bit line transistor dimension based on the calculation.

7. The method of claim 6, wherein the transistor dimension comprises a channel length.

8. The method of claim 7, wherein the channel length is longer for a transistor near a Y-decoder.

9. The method of claim 6, wherein the transistor dimension comprises a channel width.

10. The method of claim 9, wherein the channel width is narrower for a transistor near the Y-decoder.

11. The method of claim 6, wherein the transistor dimension comprises a combination of channel length and channel width.

12. The method of claim 6, further comprising determining a bit line loading after modification of the bit line transistor dimensions and determining whether the bit line loading is the desired bit line loading.

13. The method of claim 12, further comprising calculating a bit line transistor dimension and modifying the bit line transistor dimension based on the calculation, where it is determined that the bit line loading is not the desired bit line loading.

14. A method of manufacturing a memory device comprising:

determining desired bit line loading;

calculating a bit line transistor dimension that will achieve the desired bit line loading;

modifying the bit line transistor dimension based on the calculation; and

manufacturing a memory device comprising a bit line transistor that includes the modified bit line transistor dimension.

15. The method of claim 14, wherein the transistor dimension comprises a channel length.

16. The method of claim 15, wherein the channel length is longer for a transistor near a Y-decoder.

17. The method of claim 14, wherein the transistor dimension comprises a channel width.

18. The method of claim 17, wherein the channel width is narrower for a transistor near the Y-decoder.

19. The method of claim 14, wherein the transistor dimension comprises a combination of channel length and channel width.

20. A memory device comprising:

a bit line;

a first Bit Line Transistor (BLT) coupled to the bit line, the first BLT comprising a channel; and

a second BLT coupled to the bit line, the second BLT comprising a channel, the dimensions of which are different from the dimensions of the first BLT channel, wherein the channel dimensions for the first and second BLTs comprise a channel width and length, and wherein the channel width and length for the first BLT are different than the channel width for the second BLT.

21. The memory device of claim 20, wherein the channel length for the first BLT is shorter than the channel length for the second BLT.

22. The memory device of claim 20, wherein the channel width for the first BLT is wider than the channel length for the second BLT.

23. The memory device of claim 20, further comprising a Y-decoder, coupled to the first and second BLTs through a bit line and proximate to the second BLT.

24. The memory device of claim 20, wherein the first and second BLTs are in different sectors.