Nonvolatile semiconductor memory device

• US 7,286,401 B2
• Filed: 12/03/2004
• Issued: 10/23/2007
• Est. Priority Date: 12/19/2003
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamazoe, Takanori, Ishimaru, Tetsuya
• Primary Examiner(s): PHAM, LY D
• Application Number:
  US11/002,794
• Publication Number:
  US 20050135155A1
• Time in Patent Office: 1,054 Days
• Field of Search: 365/185.02, 365/185.08, 365/185.11, 365/222, 365/236, 365/230.03
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Disclosed here is a nonvolatile semiconductor memory device used to prevent data loss that might occur in unselected memory cells due to a disturbance that might occur during programming/erasing in/from those memory cells. In the nonvolatile semiconductor memory device, the number of programming/erasing operations performed in a data storage block over a programming/erasing unit of the subject nonvolatile memory is recorded in an erasing/programming counter EW CT provided in each data storage block. When the value of the erasing/programming counter reaches a predetermined value, the data storage block corresponding to the erasing/programming counter is refreshed. In the refreshing operation, the data in the data storage block is stored in a temporary storing region provided in the data storage block, then the data in a temporary storing region of the data storage area is erased and the data stored temporarily is programmed in the data storage block again.

Claims

1. A nonvolatile semiconductor memory device that includes a nonvolatile semiconductor memory array comprising nonvolatile memory cells,

wherein said memory array further includes:

refreshing blocks, each including a plurality of erasure blocks for erasing a respective plurality of said nonvolatile memory cells collectively; and

counter areas, wherein the number of counter areas equals the number of refreshing blocks, and wherein each said counter area stores a number of programming/erasing operations performed in a corresponding one of said refreshing blocks; and

wherein data in each refreshing block is stored in a buffer memory each time the number of programming/erasing operations stored in the corresponding counter area reaches a predetermined value, then the data in said refreshing block is erased completely and the data stored in the buffer memory is programmed back to each said refreshing block;

wherein if a plurality of said counter areas reach a predetermined count value, data in the corresponding refreshing blocks are then stored sequentially in a temporary storing memory, then the data in each of the corresponding refreshing blocks are erased, and said temporarily stored data are programmed back to the corresponding refreshing blocks.

2. The nonvolatile semiconductor memory device according to claim 1, wherein said memory device is selected from among one of the following:

an EEPROM;

a charge trapping type device which stores information by accumulating a charge in a trap formed in a gate insulation film;

a floating gate type which stores information by accumulating a charge in the floating gate;

an FeRAM which stores a polarizing state of a ferroelectric substance as information;

a device that stores both a low resistance state and a high resistance state of a phase change film as information; and

an MRAM which stores both low resistance and high resistance states of tunnel magnetic resistance as information.

3. The nonvolatile semiconductor memory device according to claim 1,

wherein erasing or programming of said nonvolatile memory cells is done by injecting hot carriers.

4. The nonvolatile semiconductor memory device according to claim 1,

wherein each erasure blocks comprise a plurality of single-byte nonvolatile memory cells.

5. A nonvolatile semiconductor memory device that includes a nonvolatile semiconductor memory array comprising nonvolatile memory cells,

wherein said memory array further includes:

refreshing blocks, each including a plurality of erasure blocks for erasing a respective plurality of said nonvolatile memory cells collectively; and

counter areas, wherein the number of counter areas equals the number of refreshing blocks, and wherein each said counter area stores a number of programming/erasing operations performed in a corresponding one of said refreshing blocks; and

wherein data in each refreshing block is stored in a buffer memory each time the number of programming/erasing operations stored in the corresponding counter area reaches a predetermined value, then the data in said refreshing block is erased completely and the data stored in the buffer memory is programmed back to said refreshing block;

wherein if there are a plurality of said counter areas storing at least a predetermined number of programming/erasing operations, data in subsets of the corresponding refreshing blocks are stored in temporary storing memory sequentially in a descending order of the number of performed operations, then the data in each subset of the refreshing blocks are erased, and said temporarily stored data are programmed back to said corresponding refreshing blocks.

6. The nonvolatile semiconductor memory device according to claim 5, wherein said memory device is selected from among one of the following:

an EEPROM;

a charge trapping type device which stores information by accumulating a charge in a trap formed in a gate insulation film;

a floating gate type which stores information by accumulating a charge in the floating gate;

an FeRAM which stores a polarizing state of a ferroelectric substance as information;

a device that stores both a low resistance state and a high resistance state of a phase change film as information; and

an MRAM which stores both low resistance and high resistance states of tunnel magnetic resistance as information.

7. The nonvolatile semiconductor memory device according to claim 5,

wherein erasing or programming of said nonvolatile memory cells is done by injecting hot carriers.

8. The nonvolatile semiconductor memory device according to claim 5,

wherein each erasure block comprises a plurality of single-byte nonvolatile memory cells.