High speed sensing amplifier for an MRAM cell

• US 7,286,429 B1
• Filed: 04/24/2006
• Issued: 10/23/2007
• Est. Priority Date: 04/24/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tang, Denny, Liaw, Jhon Jhy
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/379,854
• Publication Number:
  US 20070247940A1
• Time in Patent Office: 547 Days
• Field of Search: 365/209
• US Class Current: 365/209
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in low resistance state. The resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state. The resistance of the low reference cell in low resistance state has a second margin of difference from the resistance of the memory cell in low resistance state. Differential amplifiers coupled to the memory cell and the high and low reference cells provide a digital output representing the resistance state of the memory cell.

Claims

1. A circuit for sensing a resistance state of a memory cell, the memory cell being capable of switching between a high resistance state and a low resistance state, comprising:

a high reference cell in high resistance state;

a low reference cell in low resistance state;

a voltage supply for applying a predetermined voltage to the memory cell to generate an output current;

a set of differential amplifiers selectively coupled to the memory cell and the high and low reference cells; and

a sense amplifier coupled to the differential amplifiers,

wherein the resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state the first margin of difference being determined by difference in area between the memory cell and the high reference cell, and wherein the resistance of the low reference cell in low resistance state has a second margin of difference from the resistance of the memory cell in low resistance state the second margin of difference being determined by difference in area between the memory cell and the low reference cell.

2. The circuit of claim 1, wherein the first margin of difference is defined by the resistance in the high resistance state of the high reference cell being greater than the resistance in the high resistance state of the memory cell, and wherein the second margin of difference is defined by the resistance in the low resistance state of the reference memory cell being less than the resistance in the low resistance state of the memory cell.

3. The circuit of claim 1, wherein the first margin of difference is defined by the resistance in the high resistance state of the high reference cell being less than the resistance in the high resistance state of the memory cell, and wherein the second margin of difference is defined by the resistance in the low resistance state of the reference memory cell being greater than the resistance in the low resistance state of the memory cell.

4. The circuit of claim 1, wherein the set of differential amplifiers comprises:

a first differential amplifier for subtracting the first reference current from the output current to generate the first differential signal; and

a second differential amplifier for subtracting the second reference current from the output current to generate the second differential signal.

5. The circuit of claim 1 wherein the set of differential amplifiers comprises:

a first differential amplifier for receiving the first reference current and outputting a zero output;

a second differential amplifier for subtracting the second reference current from the output current;

a third differential amplifier for subtracting the first reference current from the second reference current;

a fourth differential amplifier coupled to the first and second differential amplifiers for receiving outputs therefrom to generate the first differential signal; and

a fifth differential amplifier coupled to the second and third differential amplifiers for receiving outputs therefrom to generate the second differential signal.

6. The circuit of claim 1 wherein the set of differential amplifiers comprises:

a first differential amplifier for receiving the second reference current and outputting a zero output;

a second differential amplifier for subtracting the first reference current from the output current;

a third differential amplifier for subtracting the first reference current from the second reference current;

a fourth differential amplifier coupled to the first and second differential amplifiers for receiving outputs therefrom to generate the first differential signal; and

a fifth differential amplifier coupled to the second and third differential amplifiers for receiving outputs therefrom to generate the second differential signal.

7. The circuit of claim 1, wherein the memory cell is a magneto-resistive random access memory (MRAM) cell, phase-change random access memory (PRAM) cell, or ferroelectric random access memory (FRAM) cell.

8. The circuit of claim 1, wherein the sense amplifier comprises a current mirror load for converting current signals into a voltage signal.

9. A method for sensing a resistance state of a memory cell having a high resistance state and a low resistance state, comprising:

receiving an output current reflecting a resistance of the memory cell;

receiving a first reference current reflecting the high resistance state in the high reference cell;

receiving a second reference current reflecting the low resistance state in the low reference cell;

generating a first difference signal representing the difference between the output current and the first reference current;

generating a second difference signal representing the difference between the output current and the second reference current; and

comparing the first difference signal with the second difference signal;

and generating a digital output based on the comparison representing the resistance state of the memory cell,

wherein the resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state, and wherein the resistance of the low reference cell in low resistance state the first margin of difference being determined by difference in area between the memory cell and the high reference cell, has a second margin of difference from the resistance memory of the memory cell in low resistance state the second margin of difference being determined by difference in area between the memory cell and the low reference cell.

10. The method according to claim 9, wherein the first margin of difference is defined by the resistance in the high resistance state of the high reference cell being greater than the resistance in the high resistance state of the memory cell, and wherein the second margin of difference is defined by the resistance in the low resistance state of the reference memory cell being less than the resistance in the low resistance state of the memory cell.

11. The method according to claim 9 wherein the first margin of difference is defined by the resistance in the high resistance state of the high reference cell being less than the resistance in the high resistance state of the memory cell, and wherein the second margin of difference is defined by the resistance in the low resistance state of the reference memory cell being greater than the resistance in the low resistance state of the memory cell.

12. The method according to claim 9, further comprising:

applying a predetermined voltage to the memory cell to generate the output current, to a high reference cell to generate the first reference current, and to a low reference cell to generate the second reference current.

13. The method according to claim 12, further comprising selecting the memory cell, the high reference cell, and the low reference cell, before the step of applying the predetermined voltage.

14. The method according to claim 9:

wherein the step of generating the first difference signal further comprises;

inputting the output current into a first node of a first differential amplifier,

inputting the first reference current into a second node of the first differential amplifier, and

outputting the first difference signal from the first differential amplifier by subtracting the first reference current from the output current; and

wherein the step of generating the second difference signal further comprises;

inputting the output current into a first node of a second differential amplifier,

inputting the second reference current into a second node of the second differential amplifier, and

outputting the second difference signal from the second differential amplifier by subtracting the second reference current from the output current.

15. The method according to claim 9, wherein the steps of generating the first and second difference signals further comprises:

inputting the first reference current into a first node and a second node of a first differential amplifier;

inputting the output current into a first node of a second differential amplifier, and the second reference current into a second node of the second differential amplifier; and

inputting the second reference current into a first node of a third differential amplifier, and the first reference current into a second node of the third differential amplifier;

subtracting an output of the second differential amplifier from an output of the first differential amplifier with a fourth differential amplifier to generate the first difference signal; and

subtracting an output of the third differential amplifier from an output of the second differential amplifier with a fifth differential amplifier to generate the second difference signal.

16. The method according to claim 9, wherein the step of generating the first and second difference signals further comprises:

inputting the second reference current into a first node and a second node of a first differential amplifier;

inputting the output current into a first node of a second differential amplifier, and the first reference current into a second node of the second differential amplifier; and

inputting the second reference current into a first node of a third differential amplifier, and the first reference current into a second node of the third differential amplifier;

subtracting an output of the second differential amplifier from an output of the first differential amplifier with a fourth differential amplifier to generate the first difference signal; and

subtracting an output of the third differential amplifier from an output of the second differential amplifier with a fifth differential amplifier to generate the second difference signal.

17. The method according to claim 9, wherein the comparing further comprises:

inputting the first difference signal into a first node of a sense amplifier;

inputting the second difference signal into a second node of the sense amplifier; and

outputting the digital output from the sense amplifier based on comparison between the first and second difference signals.

18. A circuit for sensing a resistance state of a memory cell coupled to a bit line and a word line, the memory cell being capable of switching between a high resistance state and a low resistance state, the circuit comprising:

a high reference cell in high resistance state, selectively coupled to the word line and a high reference bit line;

a low reference cell in low resistance state, selectively coupled to the word line and a low reference bit line, wherein the memory cell, the high reference cell and the low reference cell are selected by a selection signal on the word line;

a voltage supply for applying a predetermined voltage to the bit line, the high reference bit line and the second reference bit line to generate an output current reflecting a resistance of the memory cell, a high reference current reflecting the high resistance state of the high reference cell, and a second reference current reflecting the low resistance state of the low reference cell;

a set of differential amplifiers selectively coupled to the memory cell and the high and low reference cells; and

a sense amplifier coupled to the differential amplifiers,

wherein the resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state the first margin of difference being determined by difference in area between the memory cell and the high reference cell, and wherein the resistance of the low reference cell in low resistance state has a second margin of difference from the resistance memory of the memory cell in low resistance state the second margin of difference being determined by difference in area between the memory cell and the low reference cell.

19. The circuit of claim 18, wherein the set of differential amplifiers comprises:

a first differential amplifier for subtracting the first reference current from the output current to generate the first differential signal; and

a second differential amplifier for subtracting the second reference current from the output current to generate the second differential signal.

20. The circuit of claim 18, wherein the sense amplifier comprises a current mirror load for converting current signals into a voltage signal.