High-density memory module utilizing low-density memory components
First Claim
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1. A memory module having a first memory capacity, the memory module comprising:
- a plurality of substantially identical memory components configured as a first rank and a second rank, the memory components of the first rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another, the memory components of the second rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another;
a logic element which receives a first set of address and control signals compatible with a second memory capacity, the second memory capacity substantially equal to one-half of the first memory capacity, wherein the logic element translates the first set of address and control signals into a second set of address and control signals compatible with the first memory capacity of the memory module, the logic element transmitting the second set of address and control signals to the first rank and the second rank; and
a termination bus, each pair of memory components comprising a first memory component having a first data strobe pin, a first termination signal pin in electrical communication with the termination bus, a first termination circuit, and at least one data pin, wherein the first termination circuit selectively electrically terminates the first data strobe pin and the at least one data pin of the first memory component in response to a first signal received by the first termination signal pin from the termination bus.
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Abstract
A memory module comprises a plurality of memory components. Each memory component has a first bit width. The plurality of memory components are configured as one or more pairs of memory components. Each pair of memory components simulates a single virtual memory component having a second bit width which is twice the first bit width.
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Citations
20 Claims
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1. A memory module having a first memory capacity, the memory module comprising:
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a plurality of substantially identical memory components configured as a first rank and a second rank, the memory components of the first rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another, the memory components of the second rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another; a logic element which receives a first set of address and control signals compatible with a second memory capacity, the second memory capacity substantially equal to one-half of the first memory capacity, wherein the logic element translates the first set of address and control signals into a second set of address and control signals compatible with the first memory capacity of the memory module, the logic element transmitting the second set of address and control signals to the first rank and the second rank; and a termination bus, each pair of memory components comprising a first memory component having a first data strobe pin, a first termination signal pin in electrical communication with the termination bus, a first termination circuit, and at least one data pin, wherein the first termination circuit selectively electrically terminates the first data strobe pin and the at least one data pin of the first memory component in response to a first signal received by the first termination signal pin from the termination bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory module having a first memory capacity, the memory module comprising:
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a plurality of substantially identical memory components configured as a first rank and a second rank, the memory components of the first rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another, the memory components of the second rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another; and a logic element which receives a first set of address and control signals compatible with a second memory capacity, the second memory capacity substantially equal to one-half of the first memory capacity, wherein the logic element translates the first set of address and control signals into a second set of address and control signals compatible with the first memory capacity of the memory module, the logic element transmitting the second set of address and control signals to the first rank and the second rank, wherein each memory component has a first bit width, a first number of banks of memory locations, a first number of row address bits, and a first number of column address bits, the memory module further comprising a serial-presence-detect (SPD) device comprising data that characterizes each pair of memory components as a virtual memory component having a second bit width equal to twice the first bit width, a second number of banks of memory locations equal to the first number of banks, a second number of row address bits equal to the first number of row address bits, and a second number of column address bits equal to the first number of column address bits. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification