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Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

  • US 7,286,439 B2
  • Filed: 12/30/2004
  • Issued: 10/23/2007
  • Est. Priority Date: 12/30/2004
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit comprising:

  • a memory array comprising array lines of first and second types coupled to memory cells;

    a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type, said first hierarchical decoder circuit comprising at least two hierarchical levels of multi-headed decoder circuits.

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