Synchronous pipelined switch using serial transmission

• US 7,286,525 B1
• Filed: 06/21/2002
• Issued: 10/23/2007
• Est. Priority Date: 12/31/1997
• Status: Expired due to Fees

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Epps, Garry P., Laor, Michael
• Primary Examiner(s): Jung; Min
• Application Number:
  US10/176,819
• Time in Patent Office: 1,950 Days
• Field of Search: 370/503, 370/359, 370/360, 370/366, 370/386, 370/370, 370/380
• US Class Current: 370/359
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5674 Synchronisation, timing recovery or alignment
• CPC Class Codes: H04L 49/106 using space switching, e.g. crossbar or matrix
• CPC Class Codes: H04L 49/608 ATM switches adapted to switch variable length packets, e.g. IP packets

Abstract

The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect. The switch interconnect includes one PLL for each input interface which synchronizes to the serial input from that input interface, and one PLL for each output interface which synchronizes to the single frequency source once for all serial communication to the output interface. Similarly, the output interfaces each include a PLL which synchronizes to the serial output from the switch interconnect. The switch interconnect is coupled to the single frequency source and operates in phase therewith.

Claims

1. A method of operating an apparatus having at least one input port and at least one output port, comprising:

generating a clock signal;

transmitting serial data from said at least one input port in synchrony with said clock signal to a serial to parallel converter;

transferring said serial data as parallel data by said serial to parallel converter to a switch;

switching said parallel data at said switch in synchrony with said clock signal;

receiving said parallel data from said switch by a parallel to serial converter;

transmitting said parallel data serially from said parallel to serial converter in synchrony with said clock signal to said at least one output port; and

receiving at said at least one output port said serially transmitted data from said parallel to serial converter.

2. A method as in claim 1 further comprising:

self-synchronizing said serial to parallel converter to said transmitted serial data received at said serial to parallel converter.

3. A method as in claim 1 further comprising:

self-synchronizing a second serial to parallel converter in said at least one output port to said received serially transmitted data at said at least one output port.

4. A method as in claim 1 further comprising:

converting data from parallel to serial at said input port at a second parallel to serial converter.

5. A method as in claim 4 further comprising:

transmitting serial data from said second parallel to serial converter at a rate equal to said clock signal times the ratio of parallel inputs to serial outputs of said second parallel to serial converter.

6. A method as in claim 5 further comprising:

transmitting serial data from said second parallel to serial converter at a rate equal to 10 times said clock signal.

7. A method as in claim 1 further comprising:

converting data from serial to parallel at said output port at a second serial to parallel converter.

8. A method as in claim 7 further comprising:

transmitting parallel data from said second serial to parallel converter at a rate equal to a recovered clock signal generated in response to the receive rate of serial data into said second serial to parallel converter times the ratio of serial inputs to parallel outputs of said second serial to parallel converter.

9. A method as in claim 8 further comprising:

transmitting parallel data from said second serial to parallel converter at a rate equal to 1/10 of a recovered clock signal generated in response to the receive rate of serial data into said second serial to parallel converter.

10. A method as in claim 1 further comprising:

transmitting said data from said output port through an output register synchronized to said clock signal.

11. A method as in claim 1 further comprising:

transmitting serial data from said parallel to serial converter at a rate equal to said clock signal times the ratio of parallel inputs to serial outputs of said parallel to serial converter.

12. A method as in claim 11 further comprising:

transmitting serial data from said parallel to serial converter at a rate equal to 10 times said clock signal.

13. A method as in claim 1 further comprising:

transmitting parallel data from said serial to parallel converter at a rate equal to a recovered clock signal generated in response to the receive rate of serial data into said serial to parallel converter times the ratio of serial inputs to parallel outputs of said serial to parallel converter.

14. A method as in claim 13 further comprising:

transmitting parallel data from said serial to parallel converter at a rate equal to 1/10 of a recovered clock signal generated in response to the receive rate of serial data into said serial to parallel converter.

15. A method as in claim 1 further comprising:

synchronizing a phase-locked loop at said at least one input port to said clock source for serial communication from said at least one input port.

16. A method as in claim 1 further comprising:

synchronizing a phase-locked loop at said parallel to serial converter to said clock source for serial communication from said parallel to serial converter.

17. A method as in claim 15 or 16 further comprising:

synchronizing said phase-locked loop once for all serial communication.

18. A method as in claim 15 or 16 further comprising:

transmitting serial data at a rate equal to said clock signal times the ratio of parallel inputs to serial outputs.

19. A method as in claim 15 or 16 further comprising:

transmitting serial data at a rate equal to 10 times said clock signal.

20. A method as in claim 1 further comprising:

synchronizing a phase-locked loop at said serial to parallel converter to said transmitted serial data received at said serial to parallel converter for parallel communication from said serial to parallel converter.

21. A method as in claim 1 further comprising:

synchronizing a phase-locked loop at said at least one output port to said received serially transmitted data for parallel communication from said at least one output port.

22. A method as in claim 20 or 21 further comprising:

synchronizing said phase-locked loop once for all parallel communication.

23. A method as in claim 20 or 21 further comprising:

transmitting parallel data at a rate equal to a recovered clock signal generated in response to the receive rate of serial data times the ratio of serial inputs to parallel outputs.

24. A method as in claim 20 or 21 further comprising:

transmitting parallel data at a rate equal to 1/10 of a recovered clock signal generated in response to the receive rate of serial data.

25. A method as in claim 1 further comprising:

switching said parallel data at said switch at a rate faster than the time taken by said at least one input port to receive a data cell.

26. A method as in claim 1 further comprising:

switching said parallel data at said switch on selected data cell boundaries, thereby providing the capability to switch variable-length data.

27. A method as in claim 1 further comprising:

switching said parallel data at a synchronous switching mechanism at said switch in synchrony with said clock signal.

28. A method as in claim 1 further comprising:

switching said parallel data at a cross bar switch at said parallel switch in synchrony with said clock signal.

29. An apparatus, comprising:

a system frequency source generating a system clock signal;

at least one input interface receiving data and transmitting said data serially in synchrony with said system clock signal;

a serial to parallel converter receiving said serial data from said at least one input interface and transmitting said serial data in parallel;

a switch synchronized to said system clock signal, said switch receiving said parallel data from said serial to parallel converter and transmitting switched parallel data;

a parallel to serial converter synchronized to said system clock signal, said parallel to serial converter receiving said switched parallel data from said switch and transmitting said parallel data serially; and

at least one output interface receiving said serial data from said parallel to serial converter.

30. An apparatus as in claim 29 further comprising:

a phase-locked loop in said serial to parallel converter self-synchronized to arriving serially transmitted data; and

a register to transmit said arriving serially transmitted data in parallel in synchrony with said phase-locked loop.

31. An apparatus as in claim 29 further comprising:

a phase-locked loop in said at least on output interface self-synchronized to arriving serially transmitted data.

32. An apparatus as in claim 29 further comprising:

a second parallel to serial converter at said at least one input interface.

33. An apparatus as in claim 29 further comprising:

a second serial to parallel converter at said at least one output interface.

34. An apparatus as in claim 29 further comprising:

an output register at said at least one output interface synchronized to said system clock signal for transmitting said data.

35. An apparatus as in claim 29 further comprising:

a phase-locked loop to synchronize said at least one input interface to said system clock signal for serial communications from said at least one input interface.

36. An apparatus as in claim 29 further comprising:

a phase-locked loop to synchronize said parallel to serial converter to said system clock signal for serial communications from said parallel to serial converter.

37. An apparatus as in claim 35 or 36 further comprising:

a clock signal from said phase-locked loop, said clock signal synchronized once for all serial communication.

38. An apparatus as in claim 35 or 36 further comprising:

a clock signal from said phase-locked loop for transmitting serial data at a rate equal to said system clock signal times the ratio of parallel inputs to serial outputs.

39. An apparatus as in claim 35 or 36 further comprising:

a clock signal from said phase-locked loop for transmitting serial data at a rate equal to 10 times said system clock signal.

40. An apparatus as in claim 29 further comprising:

a phase-locked loop to synchronize said serial to parallel converter to said received serially transmitted data for parallel communications from said serial to parallel converter.

41. An apparatus as in claim 29 further comprising:

a phase-locked loop to synchronize said at least one output interface to said received serially transmitted data for parallel communications from said at least one output interface.

42. An apparatus as in claim 40 or 41 further comprising:

a clock signal from said phase-locked loop, said clock signal synchronized once for all parallel communication.

43. An apparatus as in claim 40 or 41 further comprising:

a clock signal from said phase-locked loop for transmitting parallel data at a rate equal to a recovered clock signal generated in response to the receive rate of serial data times the ratio of serial inputs to parallel outputs.

44. An apparatus as in claim 40 or 41 further comprising:

a clock signal from said phase-locked loop for transmitting parallel data at a rate equal to 1/10 of a recovered clock signal generated in response to the receive rate of serial data.

45. An apparatus as in claim 29 further comprising:

a synchronous switching mechanism as said switch.

46. An apparatus as in claim 29 further comprising:

a synchronous switching mechanism as said switch adapted to switch data at a rate faster than the time taken by said at least one input interface to receive a data cell.

47. An apparatus as in claim 29 further comprising:

a synchronous switching mechanism as said switch adapted to switch on selected data cell boundaries, thereby providing the capability to switch variable-length data.

48. An apparatus as in claim 29 further comprising:

a cross bar switch as said switch.

49. An apparatus, comprising:

a clock signal source for generating a clock signal;

means for transmitting serial data from said at least one input port in synchrony with said clock signal to a serial to parallel converter;

means for transferring said serial data as parallel data by said serial to parallel converter to a switch;

means for switching said parallel data at said switch in synchrony with said clock signal;

means for receiving said parallel data from said switch by a parallel to serial converter;

means for transmitting said parallel data serially from said parallel to serial converter in synchrony with said clock signal to said at least one output port; and

means for receiving at said at least one output port said serially transmitted data from said parallel to serial converter.

50. An apparatus as in claim 49 further comprising:

means for self-synchronizing said serial to parallel converter to said received serially transmitted data at said serial to parallel converter.

51. An apparatus as in claim 49 further comprising:

means for self-synchronizing said at least one output port to said received serially transmitted data at said at least one output port.

52. A apparatus comprising:

a clock signal source for generating a first clock signal;

at least one input interface element, said at least one input interface element having a parallel input port for receiving data cells and a serial transmitter coupled to said input port by a first parallel to serial converter, and transmitting said data cells by serial transmission, said first parallel to serial converter synchronized to said first clock signal and data cells transmitted from said at least one input interface element synchronized to said first clock signal;

a cross connect receiving serial data from said at least one input interface element at a first serial to parallel converter, said first serial to parallel converter synchronized to the received serial data transmitted from said at least one input interface element and thereby synchronized to said first clock signal, said cross connect having a switch receiving parallel data from the first serial to parallel converter, and said cross connect having a second parallel to serial converter receiving parallel data from the switch and transmitting the data from the cross connect by serial transmission, said second parallel to serial converter synchronized to said first clock signal and data cells transmitted from said cross connect synchronized to said first clock signal; and

at least one output interface element receiving serial data transmitted from said cross connect at a second serial to parallel converter, said second serial to parallel converter synchronized to the received serial data transmitted from said cross connect and thereby synchronized to said first clock signal, and an output port receiving parallel data from said second serial to parallel converter and transmitting parallel data.

53. A method of operating a switch, comprising:

generating a first clock signal;

receiving data cells as parallel data at an input port, coupling the parallel data to a first parallel to serial converter, transmitting said data cells by serial transmission to a cross connect, and synchronizing said first parallel to serial converter and said data cells transmitted from said input port to said first clock signal;

receiving by said cross connect said data cells transmitted from the input port as serial data, coupling said serial data to a first serial to parallel converter, synchronizing said first serial to parallel converter to the received serial data thereby synchronizing it to said first clock signal, coupling parallel data from said first serial to parallel converter to a synchronous switch, coupling parallel data from said switch to a second parallel to serial converter, transmitting the data by serial transmission to at least one output interface, and synchronizing said second parallel to serial converter and said data cells transmitted from said cross connect to said first clock signal; and

receiving serial data by said at least one output interface, said serial data coupled to a second serial to parallel converter located in said output interface, synchronizing said second serial to parallel converter to the serial data received by said at least one output interface thereby synchronizing it to said first clock signal, and delivering parallel data by said second serial to parallel converter to an output port of said output interface.